chufa.vhd

除法器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity chufa is

	generic
	(
		beichushu_kuan : integer := 8;
		chushu_kuan : integer := 4
	);

	port 
	( 
		beichushu :  in unsigned ((beichushu_kuan-1) downto 0);--  bei  chu  shu 
		 chushu  :  in unsigned ((chushu_kuan-1) downto 0);--chushu
		 clk	 :  in std_logic;
		 clear	 :  in std_logic;
		 shang	 :  out unsigned ((beichushu_kuan-1) downto 0);
		  yushu  :   out unsigned ((chushu_kuan-1) downto 0)
	);

end entity;

architecture chufa of chufa is



begin

	process (clk, clear)
		variable temp_zhongjian : unsigned (chushu_kuan downto 0);
	    variable temp_shang    	: unsigned ((beichushu_kuan-1)  downto 0);
	begin
		if (clear = '1') then

			shang <= (others => '0');
			yushu <= (others => '0');
			temp_shang:=(others => '0');
			temp_zhongjian:=(others => '0');
		elsif (rising_edge(clk)) then
		

			temp_shang:=(others => '0');
			temp_zhongjian:=(others => '0');
	-------------------------------------------------------------------		
	
	
	
	
			temp_zhongjian(0):=beichushu(beichushu_kuan-1);
			for i in 1 to beichushu_kuan-1 loop
				if temp_zhongjian >= chushu then
					temp_shang:= temp_shang+temp_shang+1 ;
					temp_zhongjian:=temp_zhongjian-chushu;
				else 
					temp_shang:=temp_shang+temp_shang   ;
				end if;
				temp_zhongjian:=temp_zhongjian((chushu_kuan-1) downto 0) & beichushu((beichushu_kuan-i-1));
			end loop ;
			
				if temp_zhongjian >= chushu then
					temp_shang:=temp_shang+temp_shang+1 ;
					temp_zhongjian:=temp_zhongjian-chushu;
				else 
					temp_shang:=temp_shang+temp_shang   ;
				end if;
				yushu<=temp_zhongjian(chushu_kuan-1 downto 0);
				shang<=temp_shang;
				
				
				
				
				
				
				
				
				
		end if;
	end process;


end chufa;