📄 toptest.vhd
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library ieee;
use ieee.std_logic_1164.all;
use work.roms.all;
use work.MYfunction.all;
use ieee.std_logic_unsigned.all;entity TOP_TEST is
end TOP_TEST;
architecture bench of TOP_TEST is
component ROM_TOP port( ADDR:in std_logic_vector(2 downto 0);
RD,CLK:in std_logic;
DATA_OUT:out std_logic_vector(7 downto 0));
end component; signal ADDR:std_logic_vector(2 downto 0); signal DATA_OUT:std_logic_vector(7 downto 0); signal RD,CLK1,CLK:std_logic:='0'; for DUT:ROM_TOP use entity work.ROM_TOP(BEHAVIOR); begin
DUT: ROM_TOP port map (ADDR,RD,CLK,DATA_OUT); RD<= not RD after 100 ns; CLK1<=not CLK1 after 50 ns; CLK<=CLK1 and RD; ADDR_GEN:process variable CNT:std_logic_vector(2 downto 0):="000";
begin
ADDR<=CNT; wait for 200 ns; if CNT="111" then CNT:="000"; else CNT:=CNT+1; end if; end process;
end BEnch;
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