📄 romrdtest.vhd
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library ieee;
use ieee.std_logic_1164.all;
use work.roms.all;
use work.MYfunction.all;
use ieee.std_logic_unsigned.all;entity HuffROM_TEST is
end HuffROM_TEST;
architecture bench of HuffROM_TEST is
component HUFFROM port( ADDR:in std_logic_vector(2 downto 0);
RD:in std_logic;
DATA:out std_logic_vector(7 downto 0));
end component; signal ADDR:std_logic_vector(2 downto 0); signal DATA:std_logic_vector(7 downto 0); signal RD:std_logic:='0'; for DUT:HuffROM use entity work.HuffROM(BEHAVIOR); begin
DUT: HuffROM port map (ADDR,RD,DATA); RD<= not RD after 50 ns; ADDR_GEN:process variable CNT:std_logic_vector(2 downto 0):="000";
begin
ADDR<=CNT; wait for 100 ns; if CNT="111" then CNT:="000"; else CNT:=CNT+1; end if; end process;
end BEnch;
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