countertest.vhd

来自「用于视频运动图像编码的HUFFMAN编码」· VHDL 代码 · 共 35 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity COUNTER_5_TEST is
	
end COUNTER_5_TEST;

architecture BENCH of COUNTER_5_TEST is
	
	component COUNTER_5
	port(	RST: in std_logic;
		CLK: in std_logic;
		COUNTER_Q: out std_logic_vector(4 downto 0);
		CARRY: out std_logic				 );
	end component;
	
	
	
	signal RST :std_logic:='0';
	signal CLK :std_logic:='1';
	signal CARRY :std_logic;
	signal COUNTER_Q :std_logic_vector(4 downto 0);
	
	for DUT:  COUNTER_5 use entity work.COUNTER_5(ALG);
begin
	DUT: COUNTER_5 port map (RST,CLK,COUNTER_Q,CARRY);
	RST<='1' after 60 ns;
	CLK<= not CLK after 50 ns;
	
end BENCH;