romdctest.vhd

来自「用于视频运动图像编码的HUFFMAN编码」· VHDL 代码 · 共 44 行

library ieee;
use ieee.std_logic_1164.all;
use work.romdc.all;
use work.MYfunction.all;
use ieee.std_logic_unsigned.all;

entity ROM_DC_TEST is
	
end ROM_DC_TEST;

architecture  bench of ROM_DC_TEST is
	component ROM_DC
		port(	ADDR:in std_logic_vector(7 downto 0);
			RD,CS:in std_logic;
			DATA:out std_logic_vector(20 downto 0));
	end component;
	
	signal ADDR:std_logic_vector(7 downto 0);
	signal DATA:std_logic_vector(20 downto 0);
	signal RD,CS:std_logic:='0';
	
	for DUT:ROM_DC use entity work.ROM_DC(BEHAVIOR); 
	
	
begin
	DUT: ROM_DC port map (ADDR,RD,CS,DATA);
	
	RD<= not RD after 50 ns;
	CS<=not CS after 200 ns;
	
	ADDR_GEN:process
		variable CNT:std_logic_vector(7 downto 0):="00000000";
	
	begin
		ADDR<=CNT;
		wait for 100 ns;
		if CNT="11111111" then 
			CNT:="00000000";
		else
			CNT:=CNT+1;
		end if;
	end process;
end BEnch;