📄 top.vhd
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library ieee;
use ieee.std_logic_1164.all;
use work.roms.all;
use work.MYfunction.all;
entity ROM_TOP is
port( ADDR:in std_logic_vector(2 downto 0);
RD,CLK:in std_logic;
DATA_OUT:out std_logic_vector(7 downto 0));
end ROM_TOP;
architecture BEHAVIOR of ROM_TOP is
component REG_8 port( CLK: in std_logic; D: in std_logic_vector(7 downto 0); Q: out std_logic_vector(7 downto 0)); end component; component HuffROM port( ADDR:in std_logic_vector(2 downto 0);
RD:in std_logic;
DATA:out std_logic_vector(7 downto 0));
end component; signal BUS1:
std_logic_vector(7 downto 0); for U1: HuffROM use entity work.HuffROM(behavior); for U2:REG_8 use entity work.REG_8(BEHAVIORAL); begin
U1: HuffROM port map(ADDR,RD,BUS1); U2:REG_8 port map (CLK,BUS1,DATA_OUT);end BEHAVIOR;
--configuration cfg of BEHAVIOR --for BEHAVIOR --end for;--end cfg;
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