📄 s16test.vhd
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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity SHIFTER_OUT_16_TEST is end SHIFTER_OUT_16_TEST;architecture BENCH of SHIFTER_OUT_16_TEST is component SHIFTER_OUT_16 port( CLK: in std_logic; RESET,LOAD:in std_logic; DIN: in std_logic_vector(15 downto 0); DOUT: out std_logic ); end component; signal RESET,CLK,LOAD:std_logic:='0'; signal DIN :std_logic_vector(15 downto 0); signal DOUT:std_logic; for DUT: SHIFTER_OUT_16 use entity work.SHIFTER_OUT_16(BEHAVIORAL); begin DUT: SHIFTER_OUT_16 port map(CLK,RESET,LOAD,DIN,DOUT); LOAD<=not LOAD after 2000 ns; CLK<=not CLK after 50 ns; RESET<='1' after 80 ns; process variable CNT: std_logic_vector(15 downto 0):="0000000000000000"; begin DIN<=CNT; wait for 100 ns; if CNT="10101111" then CNT:="0000000000000000"; else CNT:=CNT+1; end if; end process ; end BENCH;
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