📄 reg8.vhd
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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity REG_8 is port( CLK,RESET: in std_logic; D: in std_logic_vector(7 downto 0); Q: out std_logic_vector(7 downto 0));end REG_8;architecture BEHAVIORAL of REG_8 isbegin BEHAVIOR: process(CLK) begin if RESET='0' then Q<="00000000"; else if rising_edge(CLK) then Q<=D; else end if; end if; end process BEHAVIOR; end BEHAVIORAL;
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