htesta.vhd

用于视频运动图像编码的HUFFMAN编码

package TYPES is
	type STATES is (S0,S1,S2);
end package TYPES;


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.romac.all;
use work.romdc.all;
use work.MYfunction.all;
use work.types.all;


entity HCODER_TEST_A is
end entity HCODER_TEST_A;
	
architecture BENCH of HCODER_TEST_A is
	
	component HCODER
		port(	RESET,CLK,DATA_IN,START,SYNCHIN,DC:in std_logic;
			READY,DATA_OUT,SYNCHOUT:out std_logic);
	end component;	
	
	component SHIFTER_OUT_16
		port(	CLK:	in 	std_logic;
			RESET,LOAD:in std_logic;
			DIN:	in 	std_logic_vector(15 downto 0);
			DOUT:	out 	std_logic			);
	end component;
	 
	
	signal RESET,CLK,DATA_IN,SYNCHIN,LOADIN,LOAD:std_logic:='0';
	signal READY,DC,DATA_OUT,START,SYNCHOUT: std_logic;
	signal DIN:std_logic_vector(15 downto 0);
	
	for DUT1:HCODER use entity work.HCODER(STRUCTURAL);
	for DUT2:SHIFTER_OUT_16 use entity work.SHIFTER_OUT_16(BEHAVIORAL);
begin
	DUT1: HCODER port map (RESET,CLK,DATA_IN,START,SYNCHIN,DC,READY,DATA_OUT,SYNCHOUT);
	DUT2: SHIFTER_OUT_16 port map (LOADIN,RESET,LOAD,DIN,DATA_IN);
	DIN<="0000000000000000";
	CLK<= not CLK after 50 ns;
	LOAD<='1','0' after 200 ns;
	LOADIN<='1' after 30 ns,'0' after 50 ns;
	START<='1' after 100 ns;
	RESET<='1' after 10 ns;
	DC<='0';
	DATA_LOAD:process
	begin
		wait until READY ='1'; 
		SYNCHIN<=not SYNCHIN after 30 ns;
	end process;
	
	
		
						
end BENCH ;