📄 ram.vhd
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library ieee;
use ieee.std_logic_1164.all;
use work.myfunction.all;
entity RAM is
port( RD,WR:in std_logic;
addr:in std_logic_vector(7 downto 0);
data_i:in std_logic_vector(7 downto 0); data_o:out std_logic_vector(7 downto 0));
end RAM;
architecture beh of RAM is
type MEMORY is array(0 to 255) of std_logic_vector(7 downto 0);
signal MEM:MEMORY;
begin
READ:process(RD,ADDR)
begin
if RD='1' then
DATA_O<=MEM(vector_int(addr));
else
DATA_O<=(others=>'Z');
end if;
end process READ;
WRITE:process(WR,DATA_I)
begin
if WR='1' then
MEM(vector_int(addr))<=DATA_I; else
end if;
end process WRITE;
end Beh;
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