ramtest.vhd

来自「用于视频运动图像编码的HUFFMAN编码」· VHDL 代码 · 共 57 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.myfunction.all;

entity RAM_TEST is
	
end RAM_TEST;

architecture bench of RAM_TEST is
	component RAM 
		port(	RD,WR:in std_logic;
			addr:in std_logic_vector(7 downto 0);
			data_i:in std_logic_vector(7 downto 0);
			data_o:out std_logic_vector(7 downto 0));
	end component;
	
	signal ADDR,data_i,data_o:std_logic_vector(7 downto 0);
	signal rd,wr:std_logic;
	--signal clk:std_logic:='0';
	for dut: RAM use entity work.RAM(beh);	
begin
	dut: RAM port map (RD,WR,ADDR,DATA_I,DATA_O);
	
	
	ADDR_GEN:process
		variable CNT1:std_logic_vector(7 downto 0):="00000000";
	begin
		ADDR<=CNT1;
		wait for 100 ns;
		if CNT1= "11111111" then
			CNT1:="00000000";
		else 
			CNT1:=CNt1+1;
		end if;
	end process ADDR_GEN;
	
	DATA_GEN:process
		variable B:std_logic:='0';
		variable CNT2:std_logic_vector(7 downto 0):="00000000";
	begin
		DATA_I<=CNT2;
		WR<=B;
		RD<=not B;
		wait for 25 ns;
		B:=not B;
		if CNT2= "11111111" then
			CNT2:="00000000";
		else 
			CNT2:=CNT2+1;
		end if;
	end process DATA_GEN;
	
	
end Bench;