📄 romac.vhd
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library ieee;
use ieee.std_logic_1164.all;
use work.romac.all;
use work.MYfunction.all;
entity ROM_AC is
port( ADDR:in std_logic_vector(7 downto 0);
RD,CS:in std_logic;
DATA:out std_logic_vector(20 downto 0));
end ROM_AC;
architecture BEHAVIOR of ROM_AC is
begin
output:process(ADDR,RD) begin
if RD='1' and CS='1' then DATA<=ROM(vector_int(ADDR));
else
DATA<=(others=>'Z');
end if;
end process output;
end BEHAVIOR;
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