hcoder.vhd

用于视频运动图像编码的HUFFMAN编码

package TYPES is
	type STATES is (S0,S1,S2);
end package TYPES;


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.romac.all;
use work.romdc.all;
use work.MYfunction.all;
use work.types.all;


entity HCODER is
	port(	RESET,CLK,DATA_IN,START,SYNCHIN,DC:in std_logic;
		READY,DATA_OUT,SYNCHOUT:out std_logic);
end entity HCODER;
	
architecture STRUCTURAL of HCODER is	
	
	component HT 
		port(	START,CLK,RESET,DREADY,EQU:in std_logic;
			BUSY,READY,LATCH1,LATCH2,SYNCH2,RESET1,RESET2,RD,LOAD:out std_logic	);
	end component;
	component SHIFTER 
		port(	CLK:	in 	std_logic;
			RESET,LOAD:in std_logic;
			DIN:	in 	std_logic;
			DOUT:	out 	std_logic_vector(15 downto 0)	);
	end component;
	component REG_8 
		port(	CLK,RESET:	in 	std_logic;
			D:	in 	std_logic_vector(7 downto 0);
			Q:	out 	std_logic_vector(7 downto 0));
	
	end component;
	component ROM_DC 
		port(	ADDR:in std_logic_vector(7 downto 0);
			RD,CS:in std_logic;
			DATA:out std_logic_vector(20 downto 0));
	end component;
	component ROM_AC
		port(	ADDR:in std_logic_vector(7 downto 0);
			RD,CS:in std_logic;
			DATA:out std_logic_vector(20 downto 0));
	end component;
	component SHIFTER_OUT_8 
		port(	CLK:	in 	std_logic;
			RESET,LOAD:in std_logic;
			DIN:	in 	std_logic_vector(7 downto 0);
			DOUT:	out 	std_logic			);
	end component;
	component SHIFTER_OUT_16 	
		port(	CLK:	in 	std_logic;
			RESET,LOAD:in std_logic;
			DIN:	in 	std_logic_vector(15 downto 0);
			DOUT:	out 	std_logic			);
	end component;
	component COUNTER_5 
		port(	RST: in std_logic;
			CLK: in std_logic;
			COUNTER_Q: out std_logic_vector(4 downto 0);
			CARRY: out std_logic );
	end component;
	component MBUS
		port(	D_IN: in std_logic_vector(20 downto 0);
			D_OUT_A: out std_logic_vector(4 downto 0);
			D_OUT_B: out std_logic_vector(15 downto 0) );

	end component;

	component BUSM

		port(	D_IN: in std_logic_vector(15 downto 0);
			D_OUT_A,D_OUT_B: out std_logic_vector(7 downto 0) );

	end component;

	component REG_5

		port(	CLK,RESET:	in 	std_logic;
			D:	in 	std_logic_vector(4 downto 0);
			Q:	out 	std_logic_vector(4 downto 0));
	end component;

	

	signal COUNT0,COUNT1,COUNT2,LENGTH,COUNT,S7 :std_logic_vector( 4 downto 0);
	signal CARRY0,CARRY1,CARRY2,RESET1,RESET2,SYN1_O,SYN2_O,SYN1_I,SYN2_I,CS1,CS2,RESET1_O,RESET2_O,LOAD,SYN1_I_I,SYN2_I_I:std_logic;
	signal STATE_OUT,CURRENT_STATE,NEXT_STATE:STATES;
	signal EQU_O,READY_O,DREADY_O,BUSY_O,RD,LATCH1_O,LATCH2_O,LATCH1_O_O,LATCH2_O_O,LATCH1_I,LATCH2_I,SYNCH2_O,S9,S10,S11:std_logic;
	signal S1,S8:std_logic_vector(15 downto 0);
	signal S2,S3,S4,S5:std_logic_vector(7 downto 0);
	signal S6:std_logic_vector(20 downto 0);
	
	
	
	for U1:SHIFTER use entity work.SHIFTER(BEHAVIORAL);
	for U2,U12,U13:COUNTER_5 use entity work.COUNTER_5(ALG);
	for U3:HT use entity work.HT(BEHAVIORAL);
	for U4,U5:REG_8 use entity work.REG_8(BEHAVIORAL);
	for U6 :ROM_DC use entity work.ROM_DC(BEHAVIOR);  
	for U7 :ROM_AC use entity work.ROM_AC(BEHAVIOR);
	for U8 :MBUS use entity work.MBUS(ALG);
	for U9 :REG_5 use  entity work.REG_5(BEHAVIORAL);
	for U10 :SHIFTER_OUT_16 use  entity work.SHIFTER_OUT_16(BEHAVIORAL);
	for U11 :SHIFTER_OUT_8 use  entity work.SHIFTER_OUT_8(BEHAVIORAL);
	for U14 :BUSM use entity work.BUSM(ALG);
	
	
	
begin
	
	U1:SHIFTER port map(SYNCHIN,RESET,READY_O,DATA_IN,S1);
	U2:COUNTER_5 port map(RESET1,SYNCHIN,COUNT0,CARRY0);
	U3:HT port map (START,CLK,RESET,DREADY_O,EQU_O,BUSY_O,READY_O,LATCH1_O,LATCH2_O,SYNCH2_O,RESET1_O,RESET2_O,RD,LOAD);
	U4:REG_8 port map (LATCH1_I,RESET,S2,S4);
	U5:REG_8 port map (LATCH1_I,RESET,S3,S5);
	U6:ROM_DC port map (S4,RD,CS1,S6);
	U7:ROM_AC port map (S4,RD,CS2,S6);
	U8:MBUS port map (S6,S7,S8);
	U9:REG_5 port map (LATCH2_O,RESET2,S7,LENGTH);
	U10:SHIFTER_OUT_16 port map(SYN1_I,RESET,LOAD,S8,S9);
	U11:SHIFTER_OUT_8 port map(SYN2_I,RESET,LOAD,S5,S10);
	U12:COUNTER_5 port map (RESET2,SYN1_I_I,COUNT1,CARRY1);
	U13:COUNTER_5 port map (RESET2,SYN2_I_I,COUNT2,CARRY2);
	U14:BUSM port map (S1,S2,S3);
	
	
	
	RESET1<=RESET and RESET1_O;
	RESET2<=RESET and RESET2_O;
	SYN1_I<= SYN1_I_I or (LOAD and CLK);
	SYN2_I<= SYN2_I_I or (LOAD and CLK);
	LATCH1_I<=LATCH1_O_O and CLK;
	LATCH2_I<=LOAD and CLK;
	SYN1_I_I<=(SYN1_O and CLK);
	SYN2_I_I<=(SYN2_O and CLK);
	
	CS1<=DC;
	CS2<= not DC;
	READY<=READY_O;
	DATA_OUT<=(SYN1_O and S9) or (SYN2_O and S10);
	SYNCHOUT<=(SYN1_O and CLK) or (SYN2_O and CLK);
	DREADY_P:process(COUNT0)
	begin
		if COUNT0="10000" then
			DREADY_O<='1';
		else
			DREADY_O<='0';
		end if;
		
	end process DREADY_P;
	
	EQU_P:process(COUNT2)
	begin
		if COUNT2 ="1000" then
			EQU_O<='1';
		else
			EQU_O<='0';
		end if;
		
	end process EQU_P;
	
	LATCH1_P:process(LATCH1_O)
	begin
		if LATCH1_O='1' then
			LATCH1_O_O<=CLK;
		else
			LATCH1_O_O<='0';
			
		end if;
		
	end process LATCH1_P;
	
	LATCH2_P:process(LATCH2_O)
	begin
		if LATCH2_O='1' then
			LATCH2_O_O<='1';
		else
			LATCH2_O_O<='0';
		end if;
		
	end process LATCH2_P;
	
	SYN_P:process(SYNCH2_O,LENGTH,COUNT1)
	begin
		if SYNCH2_O ='1' then
			if COUNT1=LENGTH +1  then
				SYN1_O<='0';
				SYN2_O<='1';
			else
				SYN2_O<='0';
				SYN1_O<='1';
			end if;
		elsif SYNCH2_O ='0' then
			SYN1_O<='0';
			SYN2_O<='0';	
		end if;
	end process SYN_P;
	
						
end STRUCTURAL ;