reg5.vhd

来自「用于视频运动图像编码的HUFFMAN编码」· VHDL 代码 · 共 34 行

library ieee;
	use ieee.std_logic_1164.all;
	use ieee.std_logic_unsigned.all;
	use ieee.std_logic_arith.all;
	
	
entity REG_5 is
	
	port(	CLK,RESET:	in 	std_logic;
		D:	in 	std_logic_vector(4 downto 0);
		Q:	out 	std_logic_vector(4 downto 0));
end REG_5;

architecture BEHAVIORAL of REG_5 is
begin
	BEHAVIOR: process(CLK)
	begin
		if RESET='0' then
			Q<="00000";
		else
			if rising_edge(CLK) then
				Q<=D;
			else
			end if; 
			
		end if;
	
	end process BEHAVIOR;
	
end BEHAVIORAL;