📄 htest.vhd
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package TYPES is type STATES is (S0,S1,S2);end package TYPES;library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.romac.all;use work.romdc.all;use work.MYfunction.all;
use work.types.all;entity HCODER_TEST isend entity HCODER_TEST; architecture BENCH of HCODER_TEST is component HCODER port( RESET,CLK,DATA_IN,START,SYNCHIN,DC:in std_logic; READY,DATA_OUT,SYNCHOUT:out std_logic); end component; signal RESET,CLK,DATA_IN,SYNCHIN:std_logic:='0'; signal READY,DC,DATA_OUT,START,SYNCHOUT: std_logic; for DUT:HCODER use entity work.HCODER(STRUCTURAL);begin DUT: HCODER port map (RESET,CLK,DATA_IN,START,SYNCHIN,DC,READY,DATA_OUT,SYNCHOUT); CLK<= not CLK after 50 ns; DATA_IN<= '0'; START<='1' after 120 ns; RESET<='1' after 100 ns; DC<='0'; SYNCHIN<=not SYNCHIN after 70 ns; end BENCH ;
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