📄 counter5.vhd
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library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity COUNTER_5 is port( RST: in std_logic; CLK: in std_logic; COUNTER_Q: out std_logic_vector(4 downto 0); CARRY: out std_logic );end COUNTER_5;architecture ALG of COUNTER_5 is signal CNT1 :std_logic_vector(4 downto 0);begin CNT_PROCESS:process(RST,CLK) begin if RST='0' then CNT1<="00000"; else if CLK'event and CLK='1' then if CNT1="11111"then CNT1<="00000"; else CNT1<=CNT1+1 ; end if; else end if; end if; end process CNT_PROCESS; COUNTER_Q<=CNT1; CARRY_PROCESS:process(CNT1) begin case CNT1 is when "10000"=> CARRY<='0'; when others=>CARRY<='1'; end case; end process CARRY_PROCESS;end ALG;
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