statetest.vhd

来自「用于视频运动图像编码的HUFFMAN编码」· VHDL 代码 · 共 51 行

package TYPES is
	type STATES is (S0,S1,S2);
end package TYPES;


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.MYfunction.all;
use work.types.all;


entity HT_TEST is
	
end HT_TEST;
	
architecture BENCH of HT_TEST is
	
	component HT
		port(	START,CLK,RESET,DREADY,EQU:in std_logic;
			BUSY,READY,LATCH1,LATCH2,SYNCH2,RESET1,RESET2:out std_logic	);
	end component;
	
	
	
	
	signal START,DREADY,EQU:std_logic:='0';
	signal CLK,CLK1,RESET:std_logic:='0';
	
	signal BUSY,READY,LATCH1,LATCH2,SYNCH2,RESET1,RESET2: std_logic;
	
	for DUT: HT use entity work.HT(BEHAVIORAL); 
begin
	DUT: HT port map (START,CLK,RESET,DREADY,EQU,BUSY,READY,LATCH1,LATCH2,SYNCH2,RESET1,RESET2);
	RESET<='1' after 80 ns;
	CLK<= not CLK after 25 ns;
	CLK1<=CLK and SYNCH2;
	process
	begin
		START<='1';
		wait for 500 ns;
		EQU<='0';
		DREADY<='1';
		wait for 1000 ns;
		EQU<='1';
		wait for 100 ns;
	end process;		
	
	
end BENCH;