📄 s8.vhd
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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity SHIFTER_OUT_8 is port( CLK: in std_logic; RESET,LOAD:in std_logic; DIN: in std_logic_vector(7 downto 0); DOUT: out std_logic );end SHIFTER_OUT_8;architecture BEHAVIORAL of SHIFTER_OUT_8 is signal Q:std_logic_vector(7 downto 0); signal P:std_logic;begin DOUT<=P; BEHAVIOR: process(RESET,CLK) begin if RESET= '0' then Q<="00000000"; P<='0'; elsif CLK'event and CLK='1' then if LOAD='0' then P<=Q(7); for INDEX IN 6 downto 0 loop Q(INDEX+1)<=Q(INDEX); end loop; Q(0)<='0'; elsif LOAD='1' then Q<=DIN; end if; end if; end process BEHAVIOR; end BEHAVIORAL;
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