📄 shiftertest.vhd
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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity SHIFTER_TEST is end SHIFTER_TEST;architecture BENCH of SHIFTER_TEST is component SHIFTER port( CLK: in std_logic; RESET,LOAD:in std_logic; DIN: in std_logic; DOUT: out std_logic_vector(15 downto 0)); end component; signal RESET,CLK,LOAD:std_logic:='0'; signal DIN,SD :std_logic; signal DOUT:std_logic_vector(15 downto 0); for DUT: SHIFTER use entity work.SHIFTER(BEHAVIORAL); begin DUT: SHIFTER port map(CLK,RESET,LOAD,DIN,DOUT); LOAD<=not LOAD after 500 ns; CLK<=not CLK after 50 ns; RESET<='1' after 80 ns; process begin DIN<='0'; wait for 100 ns; DIN<='1'; wait for 200 ns; DIN<='0'; wait for 100 ns; DIN<='1'; wait for 100 ns; end process ; end BENCH;
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