📄 random.vhd
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--------- 电子系 学号:J02301 姓名:张宗旺----library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;entity RANDOM_GENERATOR is port (CLK: in std_logic; RANDOM_OUT: buffer std_logic_vector(7 downto 0));end RANDOM_GENERATOR;architecture ALG of RANDOM_GENERATOR is signal RANDOMV:integer range 0 to 255; begin process(CLK) begin if CLK'event and CLK='1' then RANDOMV<=(RANDOMV*3 + 16#51#) mod 16#100#; end if; end process; RANDOM_OUT<=conv_std_logic_vector(RANDOMV,8);end ALG;
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