timer.vhd

用于视频运动图像编码的HUFFMAN编码

---------      电子系                 学号：J02301                姓名：张宗旺----
library ieee;
	use ieee.std_logic_1164.all;
	use ieee.std_logic_unsigned.all;
	use ieee.std_logic_arith.all;
entity TIMER is
	port	(RST,CLK,KEY: in std_logic;
		OUTPUT: out std_logic_vector(5 downto 0));
		
end TIMER;

architecture ALG of TIMER is

signal KEY_OUT: std_logic_vector( 2 downto 0):="000";
signal COUNT1,TIMER_OUT:std_logic_vector(5 downto 0):="000000";
begin
	--first process--
	KEY_PROCESS:process(RST,KEY)
	begin 
	if RST='0' then
		KEY_OUT<="000";
	else
		if KEY'event and KEY='1' then
			if KEY_OUT="100" then
				KEY_OUT<="000";
			else
				KEY_OUT<=KEY_OUT+1;
			end if;
		end if;
	end if;
	end process;
	
	
	--second process--
	TIMER_PROCESS: process(CLK)
	begin
	if CLK'event and CLK='1' then
	
		case KEY_OUT is
			when "000" =>
				TIMER_OUT<="000000";
			when "001" =>
				if CLK'event and CLK='1' then
					TIMER_OUT<=TIMER_OUT+1;
				else
				end if;
			when "010" =>
				
				if CLK'event and CLK='1' then
					TIMER_OUT<=TIMER_OUT+1;
				else
				end if;	
			when others => null;
		end case;
	else 
	end if;
	end process;
	
	
	
	--third process--
	OUT_PROCESS: process(KEY_OUT)
	begin
	case KEY_OUT is
		when "000" =>
		 	OUTPUT<="000000";
		when "001" =>
		 	OUTPUT<="000000";
		when "010" =>
		 	COUNT1<=TIMER_OUT;
		 	OUTPUT<="000000";
		when "011" =>
		 	OUTPUT<=TIMER_OUT;
		when "100" =>
		 	OUTPUT<=COUNT1;	
		when others  =>null;
	end case;	 	
	end process;
	
	
end ALG;