📄 alu.vhd
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--------- 电子系 学号:J02301 姓名:张宗旺---- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use work.MYFUNCTION.all;entity ALU is port( A,B: in std_logic_vector(7 downto 0); CI:in std_logic; OP:in std_logic_vector(1 downto 0); SUM: out std_logic_vector(7 downto 0)); end ALU;architecture ALG of ALU isbegin OPORATION:process(A,B,CI,OP) begin case OP is when "00" =>SUM<=ADD(A,B,CI); when "10" =>SUM<=SHIFT(A); when others =>SUM<=A; end case; end process;end ALG;
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