📄 counter12test.vhd
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--------- 电子系 学号:J02301 姓名:张宗旺----library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity COUNTER_BENCH isend COUNTER_BENCH;architecture BENCH of COUNTER_BENCH is component COUNTER12 is port (RST,UPDOWN: in std_logic; CLK: in std_logic; COUNTER_Q: out std_logic_vector(3 downto 0)); end component; signal CLK:std_logic:='0'; signal RST,UPDOWN:std_logic; signal COUNTER_Q:std_logic_vector(3 downto 0);begin U1: entity work.COUNTER12(ALG) port map(RST,UPDOWN,CLK,COUNTER_Q); RST<='0' ,'1' after 100 ns; CLK<= not CLK after 50 ns; UPDOWN_WAVER: process begin UPDOWN<='1'; wait for 2000 ns; while true loop UPDOWN<='0'; wait for 1500 ns; UPDOWN<='1'; wait for 50 ns; end loop; end process; end BENCH;
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