📄 keytest.vhd
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--------- 电子系 学号:J02301 姓名:张宗旺----library ieee;use ieee.std_logic_1164.all;entity KEY_TEST is port( KEY_IN: in std_logic; CLK: in std_logic; TEST_OUT: out std_logic; RST:in std_logic );end KEY_TEST;architecture ALG of KEY_TEST issignal COUNTER: integer range 0 to 100;begin process(CLK,RST) begin if RST='0' then TEST_OUT<='0'; else if CLK'event and CLK='1' then if KEY_IN='1' then COUNTER<=COUNTER+1; TEST_OUT<='0' else if COUNTER<10 then COUNTER<=0; else COUNTER<=0; TEST_OUT<='1'; end if; end if; end if; end if; end process;end ALG;
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