📄 counter12.vhd
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--------- 电子系 学号:J02301 姓名:张宗旺----library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity COUNTER12 is port (RST,UPDOWN: in std_logic; CLK: in std_logic; COUNTER_Q: out std_logic_vector(3 downto 0));end COUNTER12;architecture ALG of COUNTER12 is signal CNT: std_logic_vector(3 downto 0);begin COUNT:process(RST,CLK) begin if RST='0' then CNT<="0000"; else if CLK'event and CLK='1' then if UPDOWN='1' then if CNT="1011" then CNT<="0000"; else CNT<=CNT+1; end if; else if CNT="0000" then CNT<="1011"; else CNT<=CNT-1; end if; end if; end if; end if; end process; COUNTER_Q<=CNT;end ALG;
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