📄 alutest.vhd
字号:
--------- 电子系 学号:J02301 姓名:张宗旺---- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use work.MYFUNCTION.all;entity ALU_TEST is end ALU_TEST;architecture BENCH of ALU_TEST is component ALU port( A,B: in std_logic_vector(7 downto 0); CI:in std_logic; OP:in std_logic_vector(1 downto 0); SUM: out std_logic_vector(7 downto 0)); end component; signal A,B,SUM:std_logic_vector(7 downto 0); signal CI:std_logic:='0'; signal OP:std_logic_vector(1 downto 0); for DUT:ALU use entity work.ALU(ALG);begin DUT: ALU port map(A,B,CI,OP,SUM); CI<= not CI after 100 ns; A_GEN:process variable CNT1:std_logic_vector(7 downto 0):="00000000"; begin A<=CNT1; if CNT1="11111111" then CNT1:="00000000"; else CNT1:=CNT1+1; end if; wait for 50 ns; end process A_GEN; B_GEN:process variable CNT2:std_logic_vector(7 downto 0):="00000000"; begin B<=CNT2; if CNT2="11111111" then CNT2:="00000000"; else CNT2:=CNT2+1; end if; wait for 40 ns; end process B_GEN; OP_GEN:process variable CNT3:std_logic_vector(1 downto 0):="00"; begin OP<=CNT3; if CNT3="11" then CNT3:="00"; else CNT3:=CNT3+1; end if; wait for 30 ns; end process OP_GEN; end BENCH;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -