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--------- 电子系 学号:J02301 姓名:张宗旺----library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;entity FRAME_DETECTOR is port( RST,CLK,INPUT: in std_logic; OUTPUT: out std_logic );end FRAME_DETECTOR;architecture ALG of FRAME_DETECTOR is type STATES is (S0,S1,S2,S3,S4); signal CURRENT_STATE,NEXT_STATE:STATES;begin COMPUTE_STATE: process(INPUT,CURRENT_STATE) begin NEXT_STATE<=CURRENT_STATE; case CURRENT_STATE is when S0 => if INPUT='0' then NEXT_STATE<=S1;OUTPUT<='0'; else NEXT_STATE<=S0;OUTPUT<='0'; end if; when S1 => if INPUT='1' then NEXT_STATE<=S2;OUTPUT<='0'; else NEXT_STATE<=S1;OUTPUT<='0'; end if; when S2 => if INPUT='0' then NEXT_STATE<=S3;OUTPUT<='0'; else NEXT_STATE<=S0;OUTPUT<='0'; end if; when S3 => if INPUT='1' then NEXT_STATE<=S4;OUTPUT<='0'; else NEXT_STATE<=S1;OUTPUT<='0'; end if; when S4 => if INPUT='1' then NEXT_STATE<=S0;OUTPUT<='1'; else NEXT_STATE<=S1;OUTPUT<='0'; end if; end case; end process; UPDATA: process(RST,CLK ) begin if RST='0' then CURRENT_STATE<=S0; elsif CLK'event and CLK='1' then CURRENT_STATE<=NEXT_STATE; end if; end process; end ALG;
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