testtimer.vhd

来自「用于视频运动图像编码的HUFFMAN编码」· VHDL 代码 · 共 54 行

---------      电子系                 学号：J02301                姓名：张宗旺----
library ieee;
use ieee.std_logic_1164.all;


entity TIMER_BENCH is
end TIMER_BENCH;


architecture BENCH of TIMER_BENCH is

component TIMER
	port	(RST,CLK,KEY: in std_logic;
		OUTPUT: out std_logic_vector(5 downto 0));
		
end component;


signal CLK: std_logic:='0';
signal RST: std_logic:='0';
signal KEY: std_logic;
signal OUTPUT:  std_logic_vector(5 downto 0);


for UUT_1 :TIMER use entity work.TIMER(ALG);

begin 
	UUT_1: TIMER port map(RST,CLK,KEY,OUTPUT); 
		
	RST<='1' after 100 ns;
	CLK<= not CLK after 50 ns;
	
	KEY_WAVER: process
	begin 
		
		
		KEY<='1';
		wait for 50 ns;
		KEY<='0';
		wait for 1500 ns;
		KEY<='1';
		wait for 50 ns;
		KEY<='0';
		wait for 2000 ns;
	end process;
	
	
	
end BENCH;