📄 dfftest.vhd
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--------- 电子系 学号:J02301 姓名:张宗旺----library ieee;use ieee.std_logic_1164.all;entity TESTBENCH2 isend TESTBENCH2;architecture WAVER of TESTBENCH2 iscomponent D_FF port (CLK,RST,SET,D:in std_logic; Q:out std_logic);end component;signal CLK,RST,SET,D,Q: std_logic;for all :D_FF use entity work.D_FF(ALG);begin D_FF_1: D_FF port map(CLK,RST,SET,D,Q); RST<='0' after 10 ns,'1' after 100 ns; set<='1'after 100 ns,'0' after 200 ns,'1' after 250 ns; CLK_WAVER: process begin CLK<='1'; wait for 20 ns; while true loop CLK<='1'; wait for 20 ns; CLK<='0'; wait for 50 ns; end loop; assert false report "---end---" severity error; end process; DATA_WAVER: process begin D<='1'; wait for 100 ns; D<='0'; wait for 100 ns; end process;end WAVER;
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