📄 testframe.vhd
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--------- 电子系 学号:J02301 姓名:张宗旺----library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity TEST_FRAME_DETECTOR is end TEST_FRAME_DETECTOR;architecture BENCH of TEST_FRAME_DETECTOR is component FRAME_DETECTOR port( RST,CLK,INPUT: in std_logic; OUTPUT: out std_logic ); end component; signal RST,INPUT,OUTPUT:std_logic ; signal CLK:std_logic :='0'; for UUT_1: FRAME_DETECTOR use entity work.FRAME_DETECTOR(ALG); begin UUT_1: FRAME_DETECTOR port map (RST,CLK,INPUT,OUTPUT); RST<='0','1' after 40 ns; CLK<= not CLK after 50 ns; INPUT_WAVER: process begin INPUT<='1'; wait for 30 ns; INPUT<='0'; wait for 100 ns; INPUT<='1'; wait for 100 ns; INPUT<='0'; wait for 100 ns; INPUT<='1'; wait for 200 ns; INPUT<='0'; wait for 200 ns; INPUT<='1'; wait for 100 ns; INPUT<='0'; wait for 50 ns; end process; end BENCH;
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