📄 keytestbench.vhd
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--------- 电子系 学号:J02301 姓名:张宗旺----library ieee;use ieee.std_logic_1164.all;entity KEY_BENCH isend KEY_BENCH;architecture BENCH of KEY_BENCH is --declaration of component-- component KEY_TEST port( KEY_IN: in std_logic; CLK: in std_logic; TEST_OUT: out std_logic; RST:in std_logic ); end component; --declaration of signals-- signal KEY_IN,RST,TEST_OUT:std_logic; signal CLK:std_logic:='1';begin --instantiat DUT component-- DUT1: entity work.KEY_TEST(ALG) port map(KEY_IN,CLK,TEST_OUT,RST); --stimulus-- RST<='0' after 10 ns,'1' after 100 ns; CLK<=not(CLK) after 50 ns; KEY_PROCESS: process begin KEY_IN<='0'; wait for 100 ns; KEY_IN<='1'; wait for 100 ns; KEY_IN<='0'; wait for 500 ns; KEY_IN<='1'; wait for 1100 ns; KEY_IN<='0'; wait for 1000 ns; KEY_IN<='1'; wait for 1000 ns; KEY_IN<='0'; wait for 5000 ns; KEY_IN<='0'; wait for 100 ns; end process;end BENCH;
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