xdma_multi.h

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#define XDM_DMASR_SG_BUSY_MASK      0x08000000UL /**< Scatter gather is busy */
/* @} */

/** @name Software Control Register bit fields
 *
 * The following constants provide access to the bit fields of the Software
 * Control Register(SWCR).
 * @{
 */
#define XDM_SWCR_EESGEND_MASK       0x80000000UL /**< Enable SGEND Event */
#define XDM_SWCR_ESGDA_MASK         0x40000000UL /**< Enable SG Disable Ack Event */
#define XDM_SWCR_EPWBR_MASK         0x20000000UL /**< Enable Pkt Wait Bound Event */
#define XDM_SWCR_EPCTR_MASK         0x10000000UL /**< Enable Count Threshold Event */
#define XDM_SWCR_EPD_MASK           0x08000000UL /**< Enable Pkt Done Event */
#define XDM_SWCR_EDE_MASK           0x04000000UL /**< Enable DMA Error Event */
#define XDM_SWCR_EDD_MASK           0x02000000UL /**< Enable DMA done Event */
#define XDM_SWCR_BDAEL_MASK         0x01000000UL /**< BDA Explicitly Loaded */
#define XDM_SWCR_SGE_MASK           0x00800000UL /**< Enable SG */
#define XDM_SWCR_SGD_MASK           0x00400000UL /**< Disable SG */
#define XDM_SWCR_PWB_MASK           0x000FFC00UL /**< Packet Wait Bound */
#define XDM_SWCR_PCT_MASK           0x000003FFUL /**< Packet Count Threshold */
/* @} */

/** @name Global Control/Status Register bit fields
 *
 * The following constants provide access to the bit fields of the
 * Global Control/Status Register (GCSR).
 * @{
 */
#define XDM_GCSR_GLOBAL_ENABLE_MASK    0x80000000  /**< Global Enable */
#define XDM_GCSR_ENABLE_EFO_MASK       0x00000100  /**< Enable EFIFO overflow */
#define XDM_GCSR_EFO_STATUS_MASK       0x00000001  /**< EFIFO overflow Status */
/* @} */

/** @name Global Event FIFO event bit fields
 *
 * The following constants provide access to the bit fields of the
 * Global Event FIFO events (GEFIFO).
 * @{
 */
#define XDM_GEFIFO_SGEND_MASK      0x80000000  /**< SG Operation Finished Event */
#define XDM_GEFIFO_SGDA_MASK       0x40000000  /**< SG Disable Acknowledge Event */
#define XDM_GEFIFO_PWB_MASK        0x20000000  /**< Packet Wait Bound Event */
#define XDM_GEFIFO_PCT_MASK        0x10000000  /**< Pkt Count Threshold Event */
#define XDM_GEFIFO_PD_MASK         0x08000000  /**< Packet Done Event */
#define XDM_GEFIFO_DE_MASK         0x04000000  /**< DMA Error Event */
#define XDM_GEFIFO_DD_MASK         0x02000000  /**< DMA Done Event */
#define XDM_GEFIFO_CHAN_MASK       0x00FFF000  /**< DMA Channel Event occurred on */
#define XDM_GEFIFO_EVENT_MASK      0x00000FFF  /**< DMA Channel Event Parameter */
#define XDM_GEFIFO_ENABLE_MASK     0xFE000000  /**< DMA Event Bits Mask */

#define XDM_DMA_COMPLETE        (XDM_GEFIFO_SGEND_MASK  |   \
                                 XDM_GEFIFO_SGDA_MASK   |   \
                                 XDM_GEFIFO_PWB_MASK    |   \
                                 XDM_GEFIFO_PCT_MASK    |   \
                                 XDM_GEFIFO_PD_MASK)/*     |   \
                                 XDM_GEFIFO_DD_MASK)*/
/* @} */

/**************************** Type Definitions *******************************/

/**
 * The following structure contains data which is used to maintain the
 * buffer descriptor list.
 */
typedef struct
{
   XBufDescriptor *PutPtr;         /**< Keep track of where to put into list */
   XBufDescriptor *GetPtr;         /**< Keep track of where to get from list */
   XBufDescriptor *CommitPtr;      /**< Keep track of where to commit in list */
   XBufDescriptor *LastPtr;        /**< Keep track of the last put in the list */
   Xuint16 TotalDescriptorCount;    /**< Total # of descriptors in the list */
   Xuint16 ActiveDescriptorCount;   /**< # of descriptors pointing to buffers
                                         in the buffer descriptor list */
} XDmaMulti_SgData;

/**
 * The following structure contains data which is on a per instance basis
 * for the XDmaMulti component.
 */
typedef struct
{
   Xuint32  BaseAddress;        /**< Base address of channels */
   Xuint32  IntrFifoAddress;    /**< Interrupt FIFO address */
   Xuint32  IsReady;            /**< Device is initialized and ready */
   Xuint16  ChannelCount;       /**< Number of DMA channels on device */
   Xuint32 *AddrTablePtr;       /**< Beginning of Register address table */
   XDmaMulti_SgData *SgDataTablePtr; /**< Beginning of SGDMA data structures */
} XDmaMulti;

/**
 * XDmaMulti_mSizeNeeded is used to calculate the amount of memory needed
 * in the _Initialize call.
 * (sizeof(XDmaMulti_SgData) + sizeof(Xuint32)) is the size required for
 * one channel. The first number is the size of the structure needed
 * for each channel and the second is the address pointer table.
 * Transmit and Receive are individual channels, i.e. there are two
 * DMA channels associated with each Full Duplex Peripheral channel.
 */
#define XDM_BYTES_PER_CHANNEL   (sizeof(Xuint32) + sizeof(XDmaMulti_SgData))

/***************** Macros (Inline Functions) Definitions *********************/
/** @name Macro functions
 * @{
 */
/****************************************************************************/
/**
*
* Determine the size needed for the DMA channel structure.
*
* @param    NumChannels is the total number of DMA Channels configured
*           in the hardware.
*
* @return   The size of the structure in bytes. Includes array used
*           for addresses at the beginning of the data.
*
* @note
*
* C Signature: Xuint32 XDmaMulti_mSizeNeeded(Xuint32 NumChannels);
*
*****************************************************************************/
#define XDmaMulti_mSizeNeeded(NumChannels)                                   \
    (Xuint32)((NumChannels) * XDM_BYTES_PER_CHANNEL)

/****************************************************************************/
/**
*
* Read the Global Control Register.
*
* @param    InstancePtr is the instance to be used.
*
* @return   The 32-bit value of the register.
*           <br><br>
* The control register contents of the DMA Hardware. One or more of the
* following values may be contained the register.  Each of the values are
* unique bit masks.See xdma_multi.h for a description of possible
* values. The return values are prefixed with XDM_GCSR_*.*
*
* @note
*
* C Signature: Xuint32 XDmaMulti_mGetGlobalControl(XDmaMulti *InstancePtr);
*
*****************************************************************************/
#define XDmaMulti_mGetGlobalControl(InstancePtr)                            \
        XIo_In32((InstancePtr)->BaseAddress + XDM_GCSR_REG_OFFSET)

/****************************************************************************/
/**
*
* Write the Global Control Register.
*
* @param    InstancePtr is the instance to be used.
*
* @param    Control is the 32-bit value to write to the register.
*
* @return   None
*           <br><br>
* Write the contents to the DMA Hardware. Use the XDM_GCSR_*
* constants defined in xdma_multi.h to create the bit-mask to be written to
* the register.
*
* @note
*
* C Signature: void XDmaMulti_mSetGlobalControl(XDmaMulti *InstancePtr,
*                                               Xuint32 Control);
*
*****************************************************************************/
#define XDmaMulti_mSetGlobalControl(InstancePtr, Control)                    \
        XIo_Out32((InstancePtr)->BaseAddress + XDM_GCSR_REG_OFFSET, (Control))

/****************************************************************************/
/**
*
* Read the Control Register of the given channel.
*
* @param    InstancePtr is the instance to be used.
*
* @param    Channel is the channel of interest, zero based.
*
* @return   The 32-bit value of the register
*           <br><br>
* The control register contents of the DMA channel. One or more of the
* following values may be contained the register. Each of the values are
* unique bit masks.See xdma_multi.h for a description of possible
* values. The return values are prefixed with XDM_DMACR_*.*
*
* @note
*
* C Signature: Xuint32 XDmaMulti_mGetControl(XDmaMulti *InstancePtr,
*                                            unsigned Channel);
*
*****************************************************************************/
#define XDmaMulti_mGetControl(InstancePtr, Channel)                         \
        XIo_In32((InstancePtr)->AddrTablePtr[(Channel)] +                   \
                  XDM_DMACR_REG_OFFSET)

/****************************************************************************/
/**
*
* Set the Control Register of the given channel with the provided value.
*
* @param    InstancePtr is the instance to be used.
*
* @param    Channel is the channel of interest, zero based.
*
* @param    Control is the 32-bit value to write to the register.
*           <br><br>
* Control contains the value to be written to the control register of the DMA
* channel. One or more of the following values may be contained the register.
* Each of the values are unique bit masks such that they may be ORed together
* to enable multiple bits or inverted and ANDed to disable multiple bits.
* Use the XDM_DMACR_* constants defined in xdma_multi.h to create the bit-mask
* to be written to the register.
*
* @return   None.
*
* @note
*
* C Signature: void XDmaMulti_mSetControl(XDmaMulti *InstancePtr,
*                                         unsigned Channel,
*                                         Xuint32 Control);
*
*****************************************************************************/
#define XDmaMulti_mSetControl(InstancePtr, Channel, Control)                \
        XIo_Out32((InstancePtr)->AddrTablePtr[(Channel)] +                  \
                   XDM_DMACR_REG_OFFSET, (Control))

/****************************************************************************/
/**
*
* Set the Event Enable of the given channel with the provided value.
*
* @param    InstancePtr is the instance to be used.
*
* @param    Channel is the channel of interest, zero based.
*
* @param    Enable is the 32-bit value to write to the register.
*           <br><br>
* Enable contains the event enable register contents to be written
* in the DMA channel. One or more of the following values may be contained
* the register. Each of the values are unique bit masks such that they may be
* ORed together to enable multiple bits or inverted and ANDed to disable
* multiple bits. Use the XDM_SWCR_* constants defined in xdma_multi.h to
* create the bit-mask to be written to the register.
*
* @return   None.
*
* @note
*
* C Signature: void XDmaMulti_mSetEventEnable(XDmaMulti *InstancePtr,
*                                             unsigned Channel,
*                                             Xuint32 Enable);
*
*****************************************************************************/
#define XDmaMulti_mSetEventEnable(InstancePtr, Channel, Enable)             \
        XIo_Out32((InstancePtr)->AddrTablePtr[(Channel)] +                  \
        XDM_SWCR_REG_OFFSET,                                                \
        ((XDmaMulti_mGetEventEnable((InstancePtr), (Channel)) &             \
        ~(XDM_GEFIFO_ENABLE_MASK))) | (Enable))


/****************************************************************************/
/**
*
* Read the Event Enable Register of the given channel.
*
* @param    InstancePtr is the instance to be used.