xdma_multi.h

来自「linux嵌入式系统的dma方式的实现代码」· C头文件 代码 · 共 801 行 · 第 1/3 页

*
* @param    Channel is the channel of interest, zero based.
*
* @return   The 32-bit value of the register.
*           <br><br>
* The interrupt enable of the DMA channel.  One or more of the following values
* may be contained the register. Each of the values are
* unique bit masks.See xdma_multi.h for a description of possible
* values. The return values are prefixed with XDM_SWCR_*.*
*
* @note
*
* C Signature: Xuint32 XDmaMulti_mGetEventEnable(XDmaMulti *InstancePtr,
*                                                unsigned Channel);
*
*****************************************************************************/
#define XDmaMulti_mGetEventEnable(InstancePtr, Channel)                         \
        XIo_In32((InstancePtr)->AddrTablePtr[(Channel)] + XDM_SWCR_REG_OFFSET)

/****************************************************************************/
/**
*
* Read the Event FIFO Status Register of the Device.
*
* @param    InstancePtr is the instance to be used
*
* @return   The 32-bit value of the register
*           <br><br>
* The Event FIFO Status Register contents. This register is
* a FIFO and it can only be read once per event. Once it is
* read the event is discarded and the next event appears. The user
* must ensure that this FIFO is read only once per event to maintain
* synchronization with hardware.
* <br><br>
* One or more of the following values may be contained the register.
* Each of the values are unique bit masks.See xdma_multi.h for a description
* of possible values. The return values are prefixed with XDM_GEFIFO_*.*
*
* @note
*
* C Signature: Xuint32 XDmaMulti_mGetEventStatus(XDmaMulti *InstancePtr);
*
*****************************************************************************/
#define XDmaMulti_mGetEventStatus(InstancePtr)                         \
        XIo_In32((InstancePtr)->BaseAddress + XDM_GEFIFO_OFFSET)

/****************************************************************************/
/**
*
* Determine the Channel Number of the provided Status/Event.
*
* @param    Status is the Status/Event read from Event FIFO.
*
* @return   The 32-bit value of Channel that caused the Status/Event.
*
* @note
*
* C Signature: Xuint32 XDmaMulti_mGetEventChannel(Xuint32 Status);
*
*****************************************************************************/
#define XDmaMulti_mGetEventChannel(Status)                                   \
        ((Xuint32)(((Status) & XDM_GEFIFO_CHAN_MASK) >> XDM_GEFIFO_CHAN_SHIFT))

/****************************************************************************/
/**
*
* Determine the Event Parameter of the provided Status/Event.
*
* @param    Status is the Status/Event read from Event FIFO.
*
* @return   The 32-bit value of associated Event Parameter.
*
* @note
*
* C Signature: Xuint32 XDmaMulti_mGetEventChannel(Xuint32 Status);
*
*****************************************************************************/
#define XDmaMulti_mGetEventParameter(Status)                                   \
        ((Xuint32)((Status) & XDM_GEFIFO_EVENT_MASK))

/****************************************************************************/
/**
*
* Read the Status Register of the given channel.
*
* @param    InstancePtr is the instance to be used.
*
* @param    Channel is the channel of interest, zero based.
*
* @return   The 32-bit value of the register.
*
* @note
*
* C Signature: Xuint32 XDmaMulti_mGetStatus(XDmaMulti *InstancePtr,
*                                           unsigned Channel);
*
*****************************************************************************/
#define XDmaMulti_mGetStatus(InstancePtr, Channel)                         \
        XIo_In32((InstancePtr)->AddrTablePtr[(Channel)] + XDM_DMAS_REG_OFFSET)

/****************************************************************************/
/**
*
* Set the Packet Count Threshold Value for the given channel with the provided
* value.
*
* This function sets the value of the packet count threshold register of the
* DMA channel.  It reflects the number of packets that must be sent or
* received before generating an interrupt.  This value helps implement
* a concept called "interrupt coalescing", which is used to reduce the number
* of interrupts from devices with high data rates.
*
*
* @param    InstancePtr is the instance to be used.
*
* @param    Channel is the channel of interest, zero based.
*
* @param    Threshold is the 10-bit value to write to the register.
*           Range is 0-1023, 0 is disabled.
*
* @return   None
*
* @note
*
* C Signature: void XDmaMulti_mSetPktThreshold(XDmaMulti *InstancePtr,
*                                              unsigned Channel,
*                                              Xuint32 Threshold);
*
*****************************************************************************/
#define XDmaMulti_mSetPktThreshold(InstancePtr, Channel, Threshold)         \
        XIo_Out32((InstancePtr)->AddrTablePtr[(Channel)] +                  \
        XDM_SWCR_REG_OFFSET, ((Threshold) |                                 \
         ((XIo_In32((InstancePtr)->AddrTablePtr[(Channel)] +                \
                     XDM_SWCR_REG_OFFSET)) & ~XDM_SWCR_PCT_MASK)))

/****************************************************************************/
/**
*
* Read the Packet Count Threshold of the given channel.
*
* @param    InstancePtr is the instance to be used.
*
* @param    Channel is the channel of interest, zero based.
*
* @return   The 10-bit value of the Packet Count Threshold.
*           Range is 0-1023, 0 is disabled.
*           <br><br>
* This function reads the value of the packet count threshold register of the
* DMA channel.  It reflects the number of packets that must be sent or
* received before generating an interrupt.
*
* @note
*
* C Signature: Xuint32 XDmaMulti_mGetPktThreshold(XDmaMulti *InstancePtr,
*                                                 unsigned Channel);
*
*****************************************************************************/
#define XDmaMulti_mGetPktThreshold(InstancePtr, Channel)                    \
        ((XIo_In32((InstancePtr)->AddrTablePtr[(Channel)] +                 \
            XDM_SWCR_REG_OFFSET)) & XDM_SWCR_PCT_MASK)

/****************************************************************************/
/**
*
* Set the Packet Wait Bound Value for the given channel with the provided
* value.
*
* WaitBound is the value, in milliseconds, to be stored in the wait bound
* register of the DMA channel and is a value in the range 0  - 1023.  A value
* of 0 disables the packet wait bound timer.
*
* @param    InstancePtr is the instance to be used.
*
* @param    Channel is the channel of interest, zero based.
*
* @param    WaitBound is the 10-bit value to write to the Packet Wait Bound.
*           Range is 0-1023, 0 is disabled.
*
* @return   None.
*
* @note
*
* C Signature: void XDmaMulti_mSetPktWaitBound(XDmaMulti *InstancePtr,
*                                              unsigned Channel,
*                                              Xuint32 WaitBound);
*
*****************************************************************************/
#define XDmaMulti_mSetPktWaitBound(InstancePtr, Channel, WaitBound)         \
        XIo_Out32((InstancePtr)->AddrTablePtr[(Channel)] +                  \
        XDM_SWCR_REG_OFFSET, ((WaitBound << XDM_SWCR_PWB_SHIFT) |           \
         ((XIo_In32((InstancePtr)->AddrTablePtr[(Channel)] +                \
                     XDM_SWCR_REG_OFFSET)) & ~XDM_SWCR_PWB_MASK)))


/****************************************************************************/
/**
*
* Read the Packet Wait Bound of the given channel.
*
* @param    InstancePtr is the instance to be used.
*
* @param    Channel is the channel of interest, zero based.
*
* @return   The 10-bit value of the Packet Wait Bound.
*           Range is 0-1023, 0 is disabled.
*           <br><br>
* The packet wait bound register contents for the DMA channel.
*
* @note
*
* C Signature: Xuint32 XDmaMulti_mGetPktWaitBound(XDmaMulti *InstancePtr,
*                                                 unsigned Channel);
*
*****************************************************************************/
#define XDmaMulti_mGetPktWaitBound(InstancePtr, Channel)                    \
        (((XIo_In32((InstancePtr)->AddrTablePtr[(Channel)] +                \
          XDM_SWCR_REG_OFFSET)) & XDM_SWCR_PWB_MASK) >> XDM_SWCR_PWB_SHIFT)

/*@}*/


/************************** Function Prototypes ******************************/

/**
 * Standard functions
 */
XStatus XDmaMulti_Initialize(XDmaMulti *InstancePtr,
                             Xuint32 BaseAddress,
                             Xuint32 *UserMemoryPtr,
                             Xuint16 ChannelCount);
XStatus XDmaMulti_SelfTest(XDmaMulti *InstancePtr);
void    XDmaMulti_Reset(XDmaMulti *InstancePtr, unsigned Channel);

/**
 * DMA without scatter gather functions
 */
void XDmaMulti_Transfer(XDmaMulti *InstancePtr,
                        unsigned Channel,
                        Xuint32 *SourcePtr,
                        Xuint32 *DestinationPtr,
                        Xuint32 ByteCount);

/**
 * Scatter gather functions
 */
XStatus XDmaMulti_SgStart(XDmaMulti *InstancePtr, unsigned Channel);
XStatus XDmaMulti_SgStop(XDmaMulti *InstancePtr, unsigned Channel,
                         XBufDescriptor **BufDescriptorPtr);
XStatus XDmaMulti_CreateSgList(XDmaMulti *InstancePtr,
                               unsigned Channel,
                               Xuint32 *BdMemoryPtr,
                               Xuint32 ByteCount);
Xboolean XDmaMulti_IsSgListEmpty(XDmaMulti *InstancePtr, unsigned Channel);

XStatus XDmaMulti_PutDescriptor(XDmaMulti *InstancePtr, unsigned Channel,
                                XBufDescriptor *BufDescriptorPtr);
XStatus XDmaMulti_CommitPuts(XDmaMulti *InstancePtr, unsigned Channel);
XStatus XDmaMulti_GetDescriptor(XDmaMulti *InstancePtr, unsigned Channel,
                                XBufDescriptor** BufDescriptorPtr);


#ifdef __cplusplus
}
#endif

#endif              /* end of protection macro */