cl14bitadder.vhd

利用VHDL编写的counter程序

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-- 
-- Create Date:    20:01:20 09/25/2008 
-- Design Name: Chu Kuang Liu
-- Module Name:    cl14bitadder - struc 
-- Affiliation: Prrairie View A&M University

-- Description: 4 bit full adder, structural VHDL
 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cl14bitadder is
    Port ( ci : in  STD_LOGIC;
           a : in  STD_LOGIC_VECTOR(3 downto 0);
           b : in  STD_LOGIC_VECTOR(3 downto 0);
           s : out  STD_LOGIC_VECTOR(3 downto 0);
           co : out  STD_LOGIC);
end cl14bitadder;

architecture struc of cl14bitadder is

    COMPONENT cl11bitadder
	   PORT(a : in std_logic;
		     b : in std_logic;
			 ci : in std_logic;
			  s : out std_logic;
			 co : out std_logic);
			  
		END COMPONENT;

    SIGNAL X4 : STD_LOGIC; 		
	 SIGNAL X5 : STD_LOGIC;	
    SIGNAL X6 : STD_LOGIC;	  

begin
    
    gate1 : cl11bitadder PORT MAP(a=>a(3),b=>b(3),ci=>X4,s=>s(3),co=>co);
	 gate2 : cl11bitadder PORT MAP(a=>a(2),b=>b(2),ci=>X5,s=>s(2),co=>X4);
	 gate3 : cl11bitadder PORT MAP(a=>a(1),b=>b(1),ci=>X6,s=>s(1),co=>X5);
	 gate4 : cl11bitadder PORT MAP(a=>a(0),b=>b(0),ci=>ci,s=>s(0),co=>X6);

end struc;