cl11bitadder.vhd

利用VHDL编写的counter程序

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-- 
-- Create Date:    15:37:18 09/25/2008 
-- Design Name:    Chu Kuang Liu
-- Module Name:    cl11bitadder - struc 
-- Affiliation: Prairie View A&M University

-- Description: 1 bit full adder, structural VHDL

-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cl11bitadder is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           ci : in  STD_LOGIC;
           s : out  STD_LOGIC;
           co : out  STD_LOGIC);
end cl11bitadder;

architecture struc of cl11bitadder is

    COMPONENT cl1inv
      PORT (a : IN STD_LOGIC;
            Z : OUT STD_LOGIC);
    END COMPONENT;

    COMPONENT cl1nand2
      PORT (a : IN STD_LOGIC;
		      b : IN STD_LOGIC; 
            Z : OUT STD_LOGIC);
    END COMPONENT;
	 
    COMPONENT cl1nand3
      PORT (a : IN STD_LOGIC;
		      b : IN STD_LOGIC; 
				c : IN STD_LOGIC;
            Z : OUT STD_LOGIC);
    END COMPONENT;

    COMPONENT cl1nand4
      PORT (a : IN STD_LOGIC;
		      b : IN STD_LOGIC; 
				c : IN STD_LOGIC;
				d : IN STD_LOGIC;
            Z : OUT STD_LOGIC);
    END COMPONENT;

    SIGNAL ci_n : STD_LOGIC;
	 SIGNAL a_n : STD_LOGIC;
	 SIGNAL b_n : STD_LOGIC;
	 
	 SIGNAL X0 : STD_LOGIC;
	 SIGNAL X1 : STD_LOGIC;
	 SIGNAL X2 : STD_LOGIC;
	 SIGNAL X6 : STD_LOGIC;
	 SIGNAL X7 : STD_LOGIC;
	 SIGNAL X8 : STD_LOGIC;
	 SIGNAL X9 : STD_LOGIC;
	 
begin

  gate1 : cl1inv PORT MAP (a=>ci, z=>ci_n);
  gate2 : cl1inv PORT MAP (a=>a,z=>a_n);
  gate3 : cl1inv PORT MAP (a=>b,z=>b_n);
  gate4 : cl1nand2 PORT MAP (a=>ci, b=>b, z=>X0);
  gate5 : cl1nand2 PORT MAP (a=>a, b=>b, z=>X2);
  gate6 : cl1nand2 PORT MAP (a=>ci, b=>a, z=>X1);
  gate7 : cl1nand3 PORT MAP (a=>X1, b=>X0,c=>X2,z=>co);  
  gate8 : cl1nand3 PORT MAP (a=>ci, b=>a,c=>b,z=>X8);
  gate9 : cl1nand3 PORT MAP (a=>ci_n, b=>a_n,c=>b,z=>X6);
  gate10 : cl1nand3 PORT MAP (a=>ci_n, b=>a,c=>b_n,z=>X7);
  gate11 : cl1nand3 PORT MAP (a=>ci, b=>a_n,c=>b_n,z=>X9);
  gate12 : cl1nand4 PORT MAP (a=>X8, b=>X6,C=>X7,d=>X9,z=>s);


end struc;