cl1inv.vhd

利用VHDL编写的counter程序

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-- 
-- Create Date:    13:40:39 09/25/2008 
-- Design Name:    Chu Kuang Liu
-- Module Name:    cl1inv - Behavioral 
-- Affiliation:    Prairie View A&M University    

-- Description: Inverter

-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cl1inv is
    Port ( a : in  STD_LOGIC;
           z : out  STD_LOGIC);
end cl1inv;

architecture Behavioral of cl1inv is

begin

z<=(not a) after 100ps;
end Behavioral;