cl1nand3.vhd

利用VHDL编写的counter程序

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-- 
-- Create Date:    17:09:55 09/23/2008 
-- Design Name:    Chu Kuang Liu 
-- Module Name:    cl1nand3 - Behavioral 
-- Affiliation: Prairie View A&M University 
-- Course: ELEG6103 
-- Description: 3 input nand gate, behaviral VHDL

-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cl1nand3 is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : in  STD_LOGIC;
           z : out  STD_LOGIC);
end cl1nand3;

architecture Behavioral of cl1nand3 is

begin

z<=(not(a and b and c)) after 130ps; 
end Behavioral;