dflipflop.vhd

来自「利用VHDL编写的counter程序」· VHDL 代码 · 共 46 行

----------------------------------------------------------------------------------

-- Create Date:    22:44:20 10/05/2008 
-- Design Name: Chu Kuang Liu
-- Module Name:    Dflipflop - Behavioral 
-- Affiliation: 

-- Description: D Flip-Flop
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Dflipflop is
    Port ( D : in  STD_LOGIC;
           CK : in  STD_LOGIC;
           Q : out  STD_LOGIC);
end Dflipflop;

architecture Behavioral of Dflipflop is

begin

   process(CK)
    begin 
     if (CK'event) and (CK = '1') then
       Q <= D;
	end if;
   end process;	

end Behavioral;