2to1mux.vhd

利用VHDL编写的counter程序

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-- Create Date:    21:17:10 10/03/2008 
-- Design Name: Chu Kuang Liu
-- Module Name:    TwotooneMux - Structural 
-- Affiliation: Prairie View A&M University 

-- Description: 2 to 1 Mux

-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TwotooneMux is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           s : in  STD_LOGIC;
           z : out  STD_LOGIC);
end TwotooneMux;

architecture Structural of TwotooneMux is

      COMPONENT cl1inv
         PORT (a : IN STD_LOGIC;
               Z : OUT 	STD_LOGIC);
					
      END COMPONENT;

      COMPONENT cl1nand2 
         PORT (a : IN STD_LOGIC;
			      b : IN STD_LOGIC;
               Z : OUT 	STD_LOGIC);
					
      END COMPONENT;		

      SIGNAL a_n : STD_LOGIC;
		SIGNAL X2 : STD_LOGIC;
      SIGNAL X3 : STD_LOGIC;		
				
begin

      gate1 : cl1inv PORT MAP (a=>s, z=>a_n);
      gate2 : cl1nand2 PORT MAP (a=>a, b=>s, z=>X2);
      gate3 : cl1nand2 PORT MAP (a=>b, b=>a_n, z=>X3);	
		gate4 : cl1nand2 PORT MAP (a=>X2, b=>X3, z=>z);
		
		


end Structural;