ffcounter.vhd

利用VHDL编写的counter程序

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-- Create Date:    11:25:53 10/06/2008 
-- Design Name: Chu Kuang Liu
-- Module Name:    ffcounter - Structral  
-- Affiliation: Prairie View A&M University 

-- Description: Flip-flop counter

-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ffcounter is
    Port ( Resetbar : in  STD_LOGIC;
--           X :  in  STD_LOGIC_VECTOR(3 downto 0);          
--			  Z : out STD_LOGIC_VECTOR(3 downto 0);
           CLK : in  STD_LOGIC;
--			  A : out STD_LOGIC_VECTOR(3 downto 0));
           B : in  STD_LOGIC_VECTOR(3 downto 0);
--			  sum :  out STD_LOGIC_VECTOR(3 downto 0);           
--			  Cin : in  STD_LOGIC;
			  Cout : out STD_LOGIC;
			  opmux : out STD_LOGIC_VECTOR(3 downto 0);
			  oplatch: out STD_LOGIC_VECTOR(3 downto 0);
			  opsum : out STD_LOGIC_VECTOR(3 downto 0));
			  
  end ffcounter;

architecture Structural of ffcounter is

   COMPONENT TwotooneMux 
	PORT (a : in  STD_LOGIC;
	      b : in  STD_LOGIC;
			s : in  STD_LOGIC;
			z : out STD_LOGIC);
			
	END COMPONENT;

	COMPONENT Dflipflop 
	PORT (D : in  STD_LOGIC;
	      CK : in  STD_LOGIC;
			Q : out STD_LOGIC);
			
	END COMPONENT;

   COMPONENT cl14bitadder 
	PORT (a : in  STD_LOGIC_VECTOR(3 downto 0);
	      b : in  STD_LOGIC_VECTOR(3 downto 0);
			ci : in STD_LOGIC;
			s : out  STD_LOGIC_VECTOR(3 downto 0);
			co : out STD_LOGIC);
			
	END COMPONENT;

--   SIGNAL X0 : STD_LOGIC;  
--	SIGNAL X1 : STD_LOGIC; 
--	SIGNAL X2 : STD_LOGIC; 
--   SIGNAL X3 : STD_LOGIC;  
	SIGNAL Z0 : STD_LOGIC;  
   SIGNAL Z1 : STD_LOGIC;  
   SIGNAL Z2 : STD_LOGIC;  
	SIGNAL Z3 : STD_LOGIC;  
	SIGNAL A0 : STD_LOGIC;  
   SIGNAL A1 : STD_LOGIC;  
	SIGNAL A2 : STD_LOGIC;  
	SIGNAL A3 : STD_LOGIC;  
	SIGNAL Sum0 : STD_LOGIC; 
   SIGNAL Sum1 : STD_LOGIC;
 	SIGNAL Sum2 : STD_LOGIC;
	SIGNAL Sum3 : STD_LOGIC; 

begin

   gate0 :  TwotooneMux PORT MAP (a=>Sum0, b=>'0',s=>Resetbar,z=>Z0);
	gate1 :  TwotooneMux PORT MAP (a=>Sum1, b=>'0',s=>Resetbar,z=>Z1);
	gate2 :  TwotooneMux PORT MAP (a=>Sum2, b=>'0',s=>Resetbar,z=>Z2);
	gate3 :  TwotooneMux PORT MAP (a=>Sum3, b=>'0',s=>Resetbar,z=>Z3);
	gate4 :  Dflipflop PORT MAP(D=>Z0,CK=>CLK,Q=>A0);
   gate5 :  Dflipflop PORT MAP(D=>Z1,CK=>CLK,Q=>A1);
   gate6 :  Dflipflop PORT MAP(D=>Z2,CK=>CLK,Q=>A2);
   gate7 :  Dflipflop PORT MAP(D=>Z3,CK=>CLK,Q=>A3);	
	gate8 :  cl14bitadder PORT MAP(a(3)=>A3,a(2)=>A2,a(1)=>A1,a(0)=>A0,
	                               b(3)=>B(3),b(2)=>B(2),b(1)=>B(1),b(0)=>B(0),
 			 							    s(3)=>Sum3,s(2)=>Sum2,s(1)=>Sum1,s(0)=>Sum0,ci=>'0',co=>Cout);
		
		opmux(3)<=Z3; opmux(2)<=Z2; opmux(1)<=Z1; opmux(0)<=Z0;
	   oplatch(3)<=A3; oplatch(2)<=A2; oplatch(1)<=A1; oplatch(0)<=A0;
      opsum(3)<=Sum3; opsum(2)<=Sum2; opsum(1)<=Sum1; opsum(0)<=Sum0;



end structural;