memory.s

一个开放源码

/* $Id: memory.S,v 1.4 2000/11/15 17:44:54 apc Exp $ */
/* Copyright 2000  AG Electronics Ltd. */
/* This code is distributed without warranty under the GPL v2 (see COPYING) */

#include <ppc_asm.tmpl>


.globl  bsp_init_memory

bsp_init_memory:
        mflr    r11
        lis     r10, 0x8000
        
        /* PCI Cmd */
        li      r4, 6
        ori     r3, r10, 4
        bl      __pci_config_write_16
        
        /* PCI Stat */
        ori     r3, r10, 6
        bl      __pci_config_read_16
        ori     r4, r4, 0xffff
        ori     r3, r10, 6
        bl      __pci_config_write_16
        
        /* CLK Drive */
        li      r4, 0x0300 /* Top bit will be ignored */
        ori     r3, r10, 0x74
        bl      __pci_config_write_16
        li      r4, 0xff
        ori     r3, r10, 0x73
        bl      __pci_config_write_8
        /* EUMBBAR */
        lis     r4, 0xfc00
        ori     r3, r10, 0x78
        bl      __pci_config_write_32
        /* MemStart1 */
        lis     r4, 0x6040
        ori     r4, r4, 0x2000
        ori     r3, r10, 0x80
        bl      __pci_config_write_32
        /* MemStart2 */
        lis     r4, 0xe0c0
        ori     r4, r4, 0xa080
        ori     r3, r10, 0x84
        bl      __pci_config_write_32
        /* ExtMemStart1 */
        li      r4, 0
        ori     r3, r10, 0x88
        bl      __pci_config_write_32
        /* ExtMemStart2 */
        li      r4, 0
        ori     r3, r10, 0x8c
        bl      __pci_config_write_32
        /* MemEnd1 */
        lis     r4, 0x7f5f
        ori     r4, r4, 0x3f1f
        ori     r3, r10, 0x90
        bl      __pci_config_write_32
        /* MemEnd2 */
        lis     r4, 0xffdf
        ori     r4, r4, 0xbf9f
        ori     r3, r10, 0x94
        bl      __pci_config_write_32
        /* ExtMemEnd1 */
        li      r4, 0
        ori     r3, r10, 0x98
        bl      __pci_config_write_32
        /* ExtMemEnd2 */
        li      r4, 0
        ori     r3, r10, 0x9c
        bl      __pci_config_write_32
        /* MBEN */
        li      r4, 0xf
        ori     r3, r10, 0xa0
        bl      __pci_config_write_8
        /* Page CTR */
        li      r4, 155
        ori     r3, r10, 0xa3
        lis     r7, 1
        mtctr   r7
        bl      __pci_config_write_8

        /* PICR1 */
        lis     r4, 0xff04
        ori     r4, r4, 0x1a58
        ori     r3, r10, 0xa8
        bl      __pci_config_write_32
        /* PICR2 */
        lis     r4, 0x0404
        ori     r4, r4, 0x0200
        ori     r3, r10, 0xac
        bl      __pci_config_write_32
        /* MCCR4 */
        lis     r4, 0x153a
        ori     r4, r4, 0x2229 /* Cas latency 2 */
        ori     r3, r10, 0xfc
        bl      __pci_config_write_32
        /* MCCR3 */
        lis     r4, 0x7730
        ori     r3, r10, 0xf8
        bl      __pci_config_write_32
        /* MCCR2 */
        lis     r4, 0x0500 /* ASFALL and ASRISE critical */
        ori     r4, r4, 0x17a8
        ori     r3, r10, 0xf4
        bl      __pci_config_write_32
        /* MCCR1 */
        lis     r4, 0xffe0
        ori     r3, r10, 0xf0
        lis     r7, 2
        ori     r7, r7, 0xffff
        mtctr   r7
        bl      __pci_config_write_32
        /* MCCR1 with MEMGO */
        lis     r4, 0xffe8
        ori     r3, r10, 0xf0
        bl      __pci_config_write_32
wait_mccr1:
        bdnz wait_mccr1

        mtlr    r11
        blr
        

#define RBR 0
#define THR 0
#define IER 1
#define IIR 2
#define FCR 2
#define LCR 3
#define MCR 4
#define LSR 5
#define MSR 6
#define SCR 7
#define DLL 0
#define DLM 1

        .globl  bsp_life_signs
bsp_life_signs:
        blr
        
#if 0
        lis     r7, 0xff10
        li      r8, 0x83
        stb     r8, LCR(r7)
        eieio
        sync
        li      r8, 0
        stb     r8, DLM(r7)
        li      r8, 40
        stb     r8, DLL(r7)
        li      r8, 3
        stb     r8, LCR(r7)
        li      r8, 0
        eieio
        sync
        stb     r8, IER(r7)
        li      r8, 7
        stb     r8, FCR(r7)
        li      r8, 3
        stb     r8, MCR(r7)
        li      r8, 'X'
        stb     r8, THR(r7)
        blr
#endif