ad采样模块.txt

关于通信原理课程设计中HDB3编解码的一个VERILOG源代码

// A/D采样

module mx7821(	clk,
		din,
		dout,
		rd);
input clk;
input [7:0]din;
output [7:0]dout;
output rd;

reg	rd;
reg	[3:0]cot;
reg	[7:0]dout;
wire	[3:0]count;
assign	count=cot[3:0];

always @(posedge clk)
	cot=cot+1;
		
always @(posedge clk)
	if (count==0 ||count==1 || count==2 || count==3 || count==4 || count==5 || count==6 || count==7 )
	begin
		rd=1;
	end
	else
	begin
		rd=0;
	end

always @(posedge clk)
	if (count>=12)
		dout=din;

endmodule