编码模块.txt

关于通信原理课程设计中HDB3编解码的一个VERILOG源代码

module add_v(data_in,CLK,data_out);
	input data_in;
	input CLK;
	output [1:0]data_out;
	
	reg[1:0]data_out;
	reg[1:0]counter;//0计数器,
	
	always @(posedge CLK) 
	  if(data_in==1'b1)
	  begin
		  counter<=0;
		  data_out<=2'b01;
	  end
	  else if(counter==2'b11)
	   	   begin
			    counter<=0;
			    data_out<=2'b11;
		     end
	       else begin		 
				        counter<=counter+1;
						data_out<=2'b00;
	            end
endmodule



module add_b(addv_in,addb_out,CLK);
	 input [1:0]addv_in;
	 input CLK;
	 output [1:0]addb_out;
	 
	 reg flag;
	 reg even;
	 reg [1:0]dff[3:0];
	
	 assign addb_out=(flag==0)&&(even==0)&&(dff[0]==2'b11)?2'b10:dff[3];	
			
	 always @(posedge CLK)
	 begin	 
		 dff[3]<=dff[2];
		 dff[2]<=dff[1];
		 dff[1]<=dff[0];
		 dff[0]<=addv_in;
	 end	
	 always @(posedge CLK)
	 begin
	 	 if(dff[3]==1)
		  flag=flag+1;
		 else if(dff[0]==2'b11) 
		        flag=0;
	 end		 
	 always @(posedge CLK)
	  if(dff[0]==2'b11)
		  even=1;
		else even=0;		
endmodule