filter.hier_info

vhdl抗抖动滤波器的设计

|Filter
clk => cnt1[2].CLK
clk => cnt1[1].CLK
clk => cnt1[0].CLK
clk => cnt0[2].CLK
clk => cnt0[1].CLK
clk => cnt0[0].CLK
clk => fs_out~reg0.CLK
fs_in => cnt0~5.OUTPUTSELECT
fs_in => cnt0~4.OUTPUTSELECT
fs_in => cnt0~3.OUTPUTSELECT
fs_in => fs_out~2.OUTPUTSELECT
fs_in => cnt1~5.OUTPUTSELECT
fs_in => cnt1~4.OUTPUTSELECT
fs_in => cnt1~3.OUTPUTSELECT
fs_out <= fs_out~reg0.DB_MAX_OUTPUT_PORT_TYPE