filter.vho

vhdl抗抖动滤波器的设计

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version"

-- DATE "06/10/2008 11:59:36"

-- 
-- Device: Altera EP2C5Q208C8 Package PQFP208
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, cycloneii;
USE IEEE.std_logic_1164.all;
USE cycloneii.cycloneii_components.all;

ENTITY 	Filter IS
    PORT (
	clk : IN std_logic;
	fs_in : IN std_logic;
	fs_out : OUT std_logic
	);
END Filter;

ARCHITECTURE structure OF Filter IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_fs_in : std_logic;
SIGNAL ww_fs_out : std_logic;
SIGNAL \clk~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \fs_in~combout\ : std_logic;
SIGNAL \clk~combout\ : std_logic;
SIGNAL \clk~clkctrl_outclk\ : std_logic;
SIGNAL \cnt1~154_combout\ : std_logic;
SIGNAL \cnt1~152_combout\ : std_logic;
SIGNAL \cnt1~153_combout\ : std_logic;
SIGNAL \cnt1[0]~151_combout\ : std_logic;
SIGNAL \cnt0~152_combout\ : std_logic;
SIGNAL \cnt0~150_combout\ : std_logic;
SIGNAL \cnt0~151_combout\ : std_logic;
SIGNAL \cnt0[0]~149_combout\ : std_logic;
SIGNAL \fs_out~158_combout\ : std_logic;
SIGNAL \fs_out~reg0_regout\ : std_logic;
SIGNAL cnt0 : std_logic_vector(2 DOWNTO 0);
SIGNAL cnt1 : std_logic_vector(2 DOWNTO 0);

BEGIN

ww_clk <= clk;
ww_fs_in <= fs_in;
fs_out <= ww_fs_out;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\clk~clkctrl_INCLK_bus\ <= (gnd & gnd & gnd & \clk~combout\);

\fs_in~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_fs_in,
	combout => \fs_in~combout\);

\clk~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_clk,
	combout => \clk~combout\);

\clk~clkctrl\ : cycloneii_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "falling edge")
-- pragma translate_on
PORT MAP (
	inclk => \clk~clkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \clk~clkctrl_outclk\);

\cnt1~154\ : cycloneii_lcell_comb
-- Equation(s):
-- \cnt1~154_combout\ = !\fs_in~combout\ & (cnt1(0) & !cnt1(1) # !cnt1(0) & cnt1(1) & cnt1(2))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0001010000000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \fs_in~combout\,
	datab => cnt1(0),
	datac => cnt1(1),
	datad => cnt1(2),
	combout => \cnt1~154_combout\);

\cnt1[1]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl_outclk\,
	datain => \cnt1~154_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => cnt1(1));

\cnt1~152\ : cycloneii_lcell_comb
-- Equation(s):
-- \cnt1~152_combout\ = !\fs_in~combout\ & !cnt1(0) & (cnt1(2) # !cnt1(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000010000000101",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \fs_in~combout\,
	datab => cnt1(2),
	datac => cnt1(0),
	datad => cnt1(1),
	combout => \cnt1~152_combout\);

\cnt1[0]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl_outclk\,
	datain => \cnt1~152_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => cnt1(0));

\cnt1~153\ : cycloneii_lcell_comb
-- Equation(s):
-- \cnt1~153_combout\ = !\fs_in~combout\ & (cnt1(2) $ (cnt1(0) & cnt1(1)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0001010001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \fs_in~combout\,
	datab => cnt1(0),
	datac => cnt1(2),
	datad => cnt1(1),
	combout => \cnt1~153_combout\);

\cnt1[2]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl_outclk\,
	datain => \cnt1~153_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => cnt1(2));

\cnt1[0]~151\ : cycloneii_lcell_comb
-- Equation(s):
-- \cnt1[0]~151_combout\ = cnt1(0) # cnt1(2) # !cnt1(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => cnt1(0),
	datac => cnt1(2),
	datad => cnt1(1),
	combout => \cnt1[0]~151_combout\);

\cnt0~152\ : cycloneii_lcell_comb
-- Equation(s):
-- \cnt0~152_combout\ = \fs_in~combout\ & (cnt0(0) & !cnt0(1) # !cnt0(0) & cnt0(1) & cnt0(2))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010100000001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \fs_in~combout\,
	datab => cnt0(0),
	datac => cnt0(1),
	datad => cnt0(2),
	combout => \cnt0~152_combout\);

\cnt0[1]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl_outclk\,
	datain => \cnt0~152_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => cnt0(1));

\cnt0~150\ : cycloneii_lcell_comb
-- Equation(s):
-- \cnt0~150_combout\ = \fs_in~combout\ & !cnt0(0) & (cnt0(2) # !cnt0(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000100000001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \fs_in~combout\,
	datab => cnt0(2),
	datac => cnt0(0),
	datad => cnt0(1),
	combout => \cnt0~150_combout\);

\cnt0[0]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl_outclk\,
	datain => \cnt0~150_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => cnt0(0));

\cnt0~151\ : cycloneii_lcell_comb
-- Equation(s):
-- \cnt0~151_combout\ = \fs_in~combout\ & (cnt0(2) $ (cnt0(0) & cnt0(1)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010100010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \fs_in~combout\,
	datab => cnt0(0),
	datac => cnt0(2),
	datad => cnt0(1),
	combout => \cnt0~151_combout\);

\cnt0[2]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl_outclk\,
	datain => \cnt0~151_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => cnt0(2));

\cnt0[0]~149\ : cycloneii_lcell_comb
-- Equation(s):
-- \cnt0[0]~149_combout\ = cnt0(2) # cnt0(0) # !cnt0(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => cnt0(2),
	datac => cnt0(0),
	datad => cnt0(1),
	combout => \cnt0[0]~149_combout\);

\fs_out~158\ : cycloneii_lcell_comb
-- Equation(s):
-- \fs_out~158_combout\ = \fs_in~combout\ & (\fs_out~reg0_regout\ # !\cnt0[0]~149_combout\) # !\fs_in~combout\ & \cnt1[0]~151_combout\ & \fs_out~reg0_regout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110000011101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \fs_in~combout\,
	datab => \cnt1[0]~151_combout\,
	datac => \fs_out~reg0_regout\,
	datad => \cnt0[0]~149_combout\,
	combout => \fs_out~158_combout\);

\fs_out~reg0\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl_outclk\,
	datain => \fs_out~158_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \fs_out~reg0_regout\);

\fs_out~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \fs_out~reg0_regout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_fs_out);
END structure;