filter.tan.rpt

vhdl抗抖动滤波器的设计

+--------------------------------------------------------------------+
; tsu                                                                ;
+-------+--------------+------------+-------+-------------+----------+
; Slack ; Required tsu ; Actual tsu ; From  ; To          ; To Clock ;
+-------+--------------+------------+-------+-------------+----------+
; N/A   ; None         ; 5.524 ns   ; fs_in ; fs_out~reg0 ; clk      ;
; N/A   ; None         ; 5.524 ns   ; fs_in ; cnt0[2]     ; clk      ;
; N/A   ; None         ; 5.523 ns   ; fs_in ; cnt0[0]     ; clk      ;
; N/A   ; None         ; 5.522 ns   ; fs_in ; cnt0[1]     ; clk      ;
; N/A   ; None         ; 5.414 ns   ; fs_in ; cnt1[2]     ; clk      ;
; N/A   ; None         ; 5.410 ns   ; fs_in ; cnt1[0]     ; clk      ;
; N/A   ; None         ; 5.407 ns   ; fs_in ; cnt1[1]     ; clk      ;
+-------+--------------+------------+-------+-------------+----------+


+-----------------------------------------------------------------------+
; tco                                                                   ;
+-------+--------------+------------+-------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From        ; To     ; From Clock ;
+-------+--------------+------------+-------------+--------+------------+
; N/A   ; None         ; 7.112 ns   ; fs_out~reg0 ; fs_out ; clk        ;
+-------+--------------+------------+-------------+--------+------------+


+--------------------------------------------------------------------------+
; th                                                                       ;
+---------------+-------------+-----------+-------+-------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To          ; To Clock ;
+---------------+-------------+-----------+-------+-------------+----------+
; N/A           ; None        ; -5.141 ns ; fs_in ; cnt1[1]     ; clk      ;
; N/A           ; None        ; -5.144 ns ; fs_in ; cnt1[0]     ; clk      ;
; N/A           ; None        ; -5.148 ns ; fs_in ; cnt1[2]     ; clk      ;
; N/A           ; None        ; -5.256 ns ; fs_in ; cnt0[1]     ; clk      ;
; N/A           ; None        ; -5.257 ns ; fs_in ; cnt0[0]     ; clk      ;
; N/A           ; None        ; -5.258 ns ; fs_in ; fs_out~reg0 ; clk      ;
; N/A           ; None        ; -5.258 ns ; fs_in ; cnt0[2]     ; clk      ;
+---------------+-------------+-----------+-------+-------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
    Info: Processing started: Tue Jun 10 11:59:34 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Filter -c Filter --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 340.02 MHz between source register "cnt1[0]" and destination register "fs_out~reg0"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.217 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y12_N21; Fanout = 4; REG Node = 'cnt1[0]'
            Info: 2: + IC(0.474 ns) + CELL(0.651 ns) = 1.125 ns; Loc. = LCCOMB_X27_Y12_N26; Fanout = 1; COMB Node = 'cnt1[0]~151'
            Info: 3: + IC(0.360 ns) + CELL(0.624 ns) = 2.109 ns; Loc. = LCCOMB_X27_Y12_N4; Fanout = 1; COMB Node = 'fs_out~158'
            Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 2.217 ns; Loc. = LCFF_X27_Y12_N5; Fanout = 2; REG Node = 'fs_out~reg0'
            Info: Total cell delay = 1.383 ns ( 62.38 % )
            Info: Total interconnect delay = 0.834 ns ( 37.62 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.809 ns
                Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.860 ns) + CELL(0.666 ns) = 2.809 ns; Loc. = LCFF_X27_Y12_N5; Fanout = 2; REG Node = 'fs_out~reg0'
                Info: Total cell delay = 1.806 ns ( 64.29 % )
                Info: Total interconnect delay = 1.003 ns ( 35.71 % )
            Info: - Longest clock path from clock "clk" to source register is 2.809 ns
                Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.860 ns) + CELL(0.666 ns) = 2.809 ns; Loc. = LCFF_X27_Y12_N21; Fanout = 4; REG Node = 'cnt1[0]'
                Info: Total cell delay = 1.806 ns ( 64.29 % )
                Info: Total interconnect delay = 1.003 ns ( 35.71 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "fs_out~reg0" (data pin = "fs_in", clock pin = "clk") is 5.524 ns
    Info: + Longest pin to register delay is 8.373 ns
        Info: 1: + IC(0.000 ns) + CELL(1.005 ns) = 1.005 ns; Loc. = PIN_6; Fanout = 7; PIN Node = 'fs_in'
        Info: 2: + IC(6.609 ns) + CELL(0.651 ns) = 8.265 ns; Loc. = LCCOMB_X27_Y12_N4; Fanout = 1; COMB Node = 'fs_out~158'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.373 ns; Loc. = LCFF_X27_Y12_N5; Fanout = 2; REG Node = 'fs_out~reg0'
        Info: Total cell delay = 1.764 ns ( 21.07 % )
        Info: Total interconnect delay = 6.609 ns ( 78.93 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.809 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.860 ns) + CELL(0.666 ns) = 2.809 ns; Loc. = LCFF_X27_Y12_N5; Fanout = 2; REG Node = 'fs_out~reg0'
        Info: Total cell delay = 1.806 ns ( 64.29 % )
        Info: Total interconnect delay = 1.003 ns ( 35.71 % )
Info: tco from clock "clk" to destination pin "fs_out" through register "fs_out~reg0" is 7.112 ns
    Info: + Longest clock path from clock "clk" to source register is 2.809 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.860 ns) + CELL(0.666 ns) = 2.809 ns; Loc. = LCFF_X27_Y12_N5; Fanout = 2; REG Node = 'fs_out~reg0'
        Info: Total cell delay = 1.806 ns ( 64.29 % )
        Info: Total interconnect delay = 1.003 ns ( 35.71 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 3.999 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y12_N5; Fanout = 2; REG Node = 'fs_out~reg0'
        Info: 2: + IC(0.709 ns) + CELL(3.290 ns) = 3.999 ns; Loc. = PIN_151; Fanout = 0; PIN Node = 'fs_out'
        Info: Total cell delay = 3.290 ns ( 82.27 % )
        Info: Total interconnect delay = 0.709 ns ( 17.73 % )
Info: th for register "cnt1[1]" (data pin = "fs_in", clock pin = "clk") is -5.141 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.809 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.860 ns) + CELL(0.666 ns) = 2.809 ns; Loc. = LCFF_X27_Y12_N11; Fanout = 4; REG Node = 'cnt1[1]'
        Info: Total cell delay = 1.806 ns ( 64.29 % )
        Info: Total interconnect delay = 1.003 ns ( 35.71 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 8.256 ns
        Info: 1: + IC(0.000 ns) + CELL(1.005 ns) = 1.005 ns; Loc. = PIN_6; Fanout = 7; PIN Node = 'fs_in'
        Info: 2: + IC(6.609 ns) + CELL(0.534 ns) = 8.148 ns; Loc. = LCCOMB_X27_Y12_N10; Fanout = 1; COMB Node = 'cnt1~154'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.256 ns; Loc. = LCFF_X27_Y12_N11; Fanout = 4; REG Node = 'cnt1[1]'
        Info: Total cell delay = 1.647 ns ( 19.95 % )
        Info: Total interconnect delay = 6.609 ns ( 80.05 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 114 megabytes of memory during processing
    Info: Processing ended: Tue Jun 10 11:59:35 2008
    Info: Elapsed time: 00:00:01