filter.vhd.bak

vhdl抗抖动滤波器的设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity Filter is
port(
	clk : in std_logic;
	fs_in : in std_logic;
	fs_out : out std_logic
	);
end Filter;

architecture behave of Filter is
begin
	process(clk)
	variable cnt0 : integer range 0 to 7;
	variable cnt1 : integer range 0 to 7;
	begin
		if rising_edge(clk) then
			if fs_in = '1' then
				cnt1 := 0;
				if cnt0 = 7 then
					fs_out <= '1';
					cnt0 := 0;
				else
					cnt0 := cnt0 + 1;
				end if;
			else
				cnt0 := 0;
				if cnt1 = 7 then
					fs_out <= '0';
					cnt1 := 0;
				else
					cnt1 := cnt1 + 1;
				end if;
			end if;
		end if;
	end process;
end behave;