fsk.fit.qmsg

通信系统的FSK调制程序

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.692 ns register register " "Info: Estimated most critical path is register to register delay of 1.692 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FSK_Demod:inst2\|m\[1\] 1 REG LAB_X27_Y5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X27_Y5; Fanout = 3; REG Node = 'FSK_Demod:inst2\|m\[1\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_Demod:inst2|m[1] } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.624 ns) 0.881 ns FSK_Demod:inst2\|LessThan1~24 2 COMB LAB_X27_Y5 1 " "Info: 2: + IC(0.257 ns) + CELL(0.624 ns) = 0.881 ns; Loc. = LAB_X27_Y5; Fanout = 1; COMB Node = 'FSK_Demod:inst2\|LessThan1~24'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.881 ns" { FSK_Demod:inst2|m[1] FSK_Demod:inst2|LessThan1~24 } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.187 ns) + CELL(0.624 ns) 1.692 ns FSK_Demod:inst2\|Demod 3 REG LAB_X27_Y5 1 " "Info: 3: + IC(0.187 ns) + CELL(0.624 ns) = 1.692 ns; Loc. = LAB_X27_Y5; Fanout = 1; REG Node = 'FSK_Demod:inst2\|Demod'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { FSK_Demod:inst2|LessThan1~24 FSK_Demod:inst2|Demod } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.248 ns ( 73.76 % ) " "Info: Total cell delay = 1.248 ns ( 73.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.444 ns ( 26.24 % ) " "Info: Total interconnect delay = 0.444 ns ( 26.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.692 ns" { FSK_Demod:inst2|m[1] FSK_Demod:inst2|LessThan1~24 FSK_Demod:inst2|Demod } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X14_Y0 X28_Y14 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X14_Y0 to location X28_Y14" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "3 " "Warning: Found 3 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FSK_out 0 " "Info: Pin \"FSK_out\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Demod 0 " "Info: Pin \"Demod\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led 0 " "Info: Pin \"led\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/My_Design/FPGA/FSK/FSK.fit.smsg " "Info: Generated suppressed messages file E:/My_Design/FPGA/FSK/FSK.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "178 " "Info: Allocated 178 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 12 10:23:28 2008 " "Info: Processing ended: Thu Jun 12 10:23:28 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}