prev_cmp_fsk.tan.qmsg

通信系统的FSK调制程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register FSK_Demod:inst2\|m\[1\] register FSK_Demod:inst2\|Demod 151.56 MHz 6.598 ns Internal " "Info: Clock \"clk\" has Internal fmax of 151.56 MHz between source register \"FSK_Demod:inst2\|m\[1\]\" and destination register \"FSK_Demod:inst2\|Demod\" (period= 6.598 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.541 ns + Longest register register " "Info: + Longest register to register delay is 1.541 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FSK_Demod:inst2\|m\[1\] 1 REG LCFF_X1_Y5_N31 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y5_N31; Fanout = 3; REG Node = 'FSK_Demod:inst2\|m\[1\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_Demod:inst2|m[1] } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.653 ns) + CELL(0.319 ns) 0.972 ns FSK_Demod:inst2\|LessThan1~24 2 COMB LCCOMB_X1_Y5_N22 1 " "Info: 2: + IC(0.653 ns) + CELL(0.319 ns) = 0.972 ns; Loc. = LCCOMB_X1_Y5_N22; Fanout = 1; COMB Node = 'FSK_Demod:inst2\|LessThan1~24'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.972 ns" { FSK_Demod:inst2|m[1] FSK_Demod:inst2|LessThan1~24 } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.363 ns) + CELL(0.206 ns) 1.541 ns FSK_Demod:inst2\|Demod 3 REG LCCOMB_X1_Y5_N24 1 " "Info: 3: + IC(0.363 ns) + CELL(0.206 ns) = 1.541 ns; Loc. = LCCOMB_X1_Y5_N24; Fanout = 1; REG Node = 'FSK_Demod:inst2\|Demod'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.569 ns" { FSK_Demod:inst2|LessThan1~24 FSK_Demod:inst2|Demod } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.525 ns ( 34.07 % ) " "Info: Total cell delay = 0.525 ns ( 34.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.016 ns ( 65.93 % ) " "Info: Total interconnect delay = 1.016 ns ( 65.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.541 ns" { FSK_Demod:inst2|m[1] FSK_Demod:inst2|LessThan1~24 FSK_Demod:inst2|Demod } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "1.541 ns" { FSK_Demod:inst2|m[1] {} FSK_Demod:inst2|LessThan1~24 {} FSK_Demod:inst2|Demod {} } { 0.000ns 0.653ns 0.363ns } { 0.000ns 0.319ns 0.206ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.118 ns - Smallest " "Info: - Smallest clock skew is -0.118 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.455 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 5.455 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.985 ns) 0.985 ns clk 1 CLK PIN_32 9 " "Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_32; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 128 -120 48 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.940 ns) + CELL(0.970 ns) 2.895 ns FSK_Demod:inst2\|cnt\[4\] 2 REG LCFF_X1_Y5_N15 3 " "Info: 2: + IC(0.940 ns) + CELL(0.970 ns) = 2.895 ns; Loc. = LCFF_X1_Y5_N15; Fanout = 3; REG Node = 'FSK_Demod:inst2\|cnt\[4\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.910 ns" { clk FSK_Demod:inst2|cnt[4] } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.650 ns) + CELL(0.206 ns) 3.751 ns FSK_Demod:inst2\|LessThan0~108 3 COMB LCCOMB_X1_Y5_N4 1 " "Info: 3: + IC(0.650 ns) + CELL(0.206 ns) = 3.751 ns; Loc. = LCCOMB_X1_Y5_N4; Fanout = 1; COMB Node = 'FSK_Demod:inst2\|LessThan0~108'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.856 ns" { FSK_Demod:inst2|cnt[4] FSK_Demod:inst2|LessThan0~108 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.362 ns) + CELL(0.370 ns) 4.483 ns FSK_Demod:inst2\|LessThan0~109 4 COMB LCCOMB_X1_Y5_N2 4 " "Info: 4: + IC(0.362 ns) + CELL(0.370 ns) = 4.483 ns; Loc. = LCCOMB_X1_Y5_N2; Fanout = 4; COMB Node = 'FSK_Demod:inst2\|LessThan0~109'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.732 ns" { FSK_Demod:inst2|LessThan0~108 FSK_Demod:inst2|LessThan0~109 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.383 ns) + CELL(0.589 ns) 5.455 ns FSK_Demod:inst2\|Demod 5 REG LCCOMB_X1_Y5_N24 1 " "Info: 5: + IC(0.383 ns) + CELL(0.589 ns) = 5.455 ns; Loc. = LCCOMB_X1_Y5_N24; Fanout = 1; REG Node = 'FSK_Demod:inst2\|Demod'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.972 ns" { FSK_Demod:inst2|LessThan0~109 FSK_Demod:inst2|Demod } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.120 ns ( 57.20 % ) " "Info: Total cell delay = 3.120 ns ( 57.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.335 ns ( 42.80 % ) " "Info: Total interconnect delay = 2.335 ns ( 42.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.455 ns" { clk FSK_Demod:inst2|cnt[4] FSK_Demod:inst2|LessThan0~108 FSK_Demod:inst2|LessThan0~109 FSK_Demod:inst2|Demod } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "5.455 ns" { clk {} clk~combout {} FSK_Demod:inst2|cnt[4] {} FSK_Demod:inst2|LessThan0~108 {} FSK_Demod:inst2|LessThan0~109 {} FSK_Demod:inst2|Demod {} } { 0.000ns 0.000ns 0.940ns 0.650ns 0.362ns 0.383ns } { 0.000ns 0.985ns 0.970ns 0.206ns 0.370ns 0.589ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.573 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 5.573 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.985 ns) 0.985 ns clk 1 CLK PIN_32 9 " "Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_32; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 128 -120 48 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.940 ns) + CELL(0.970 ns) 2.895 ns FSK_Mod:inst1\|FSK_out 2 REG LCFF_X1_Y5_N27 2 " "Info: 2: + IC(0.940 ns) + CELL(0.970 ns) = 2.895 ns; Loc. = LCFF_X1_Y5_N27; Fanout = 2; REG Node = 'FSK_Mod:inst1\|FSK_out'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.910 ns" { clk FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.189 ns) + CELL(0.000 ns) 4.084 ns FSK_Mod:inst1\|FSK_out~clkctrl 3 COMB CLKCTRL_G2 3 " "Info: 3: + IC(1.189 ns) + CELL(0.000 ns) = 4.084 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'FSK_Mod:inst1\|FSK_out~clkctrl'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.189 ns" { FSK_Mod:inst1|FSK_out FSK_Mod:inst1|FSK_out~clkctrl } "NODE_NAME" } } { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.823 ns) + CELL(0.666 ns) 5.573 ns FSK_Demod:inst2\|m\[1\] 4 REG LCFF_X1_Y5_N31 3 " "Info: 4: + IC(0.823 ns) + CELL(0.666 ns) = 5.573 ns; Loc. = LCFF_X1_Y5_N31; Fanout = 3; REG Node = 'FSK_Demod:inst2\|m\[1\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.489 ns" { FSK_Mod:inst1|FSK_out~clkctrl FSK_Demod:inst2|m[1] } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.621 ns ( 47.03 % ) " "Info: Total cell delay = 2.621 ns ( 47.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.952 ns ( 52.97 % ) " "Info: Total interconnect delay = 2.952 ns ( 52.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.573 ns" { clk FSK_Mod:inst1|FSK_out FSK_Mod:inst1|FSK_out~clkctrl FSK_Demod:inst2|m[1] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "5.573 ns" { clk {} clk~combout {} FSK_Mod:inst1|FSK_out {} FSK_Mod:inst1|FSK_out~clkctrl {} FSK_Demod:inst2|m[1] {} } { 0.000ns 0.000ns 0.940ns 1.189ns 0.823ns } { 0.000ns 0.985ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.455 ns" { clk FSK_Demod:inst2|cnt[4] FSK_Demod:inst2|LessThan0~108 FSK_Demod:inst2|LessThan0~109 FSK_Demod:inst2|Demod } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "5.455 ns" { clk {} clk~combout {} FSK_Demod:inst2|cnt[4] {} FSK_Demod:inst2|LessThan0~108 {} FSK_Demod:inst2|LessThan0~109 {} FSK_Demod:inst2|Demod {} } { 0.000ns 0.000ns 0.940ns 0.650ns 0.362ns 0.383ns } { 0.000ns 0.985ns 0.970ns 0.206ns 0.370ns 0.589ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.573 ns" { clk FSK_Mod:inst1|FSK_out FSK_Mod:inst1|FSK_out~clkctrl FSK_Demod:inst2|m[1] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "5.573 ns" { clk {} clk~combout {} FSK_Mod:inst1|FSK_out {} FSK_Mod:inst1|FSK_out~clkctrl {} FSK_Demod:inst2|m[1] {} } { 0.000ns 0.000ns 0.940ns 1.189ns 0.823ns } { 0.000ns 0.985ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 26 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.336 ns + " "Info: + Micro setup delay of destination is 1.336 ns" {  } { { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 9 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 26 -1 0 } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 9 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.541 ns" { FSK_Demod:inst2|m[1] FSK_Demod:inst2|LessThan1~24 FSK_Demod:inst2|Demod } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "1.541 ns" { FSK_Demod:inst2|m[1] {} FSK_Demod:inst2|LessThan1~24 {} FSK_Demod:inst2|Demod {} } { 0.000ns 0.653ns 0.363ns } { 0.000ns 0.319ns 0.206ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.455 ns" { clk FSK_Demod:inst2|cnt[4] FSK_Demod:inst2|LessThan0~108 FSK_Demod:inst2|LessThan0~109 FSK_Demod:inst2|Demod } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "5.455 ns" { clk {} clk~combout {} FSK_Demod:inst2|cnt[4] {} FSK_Demod:inst2|LessThan0~108 {} FSK_Demod:inst2|LessThan0~109 {} FSK_Demod:inst2|Demod {} } { 0.000ns 0.000ns 0.940ns 0.650ns 0.362ns 0.383ns } { 0.000ns 0.985ns 0.970ns 0.206ns 0.370ns 0.589ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.573 ns" { clk FSK_Mod:inst1|FSK_out FSK_Mod:inst1|FSK_out~clkctrl FSK_Demod:inst2|m[1] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "5.573 ns" { clk {} clk~combout {} FSK_Mod:inst1|FSK_out {} FSK_Mod:inst1|FSK_out~clkctrl {} FSK_Demod:inst2|m[1] {} } { 0.000ns 0.000ns 0.940ns 1.189ns 0.823ns } { 0.000ns 0.985ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 1 " "Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "FSK_Demod:inst2\|cnt\[4\] FSK_Demod:inst2\|m\[0\] clk 45 ps " "Info: Found hold time violation between source  pin or register \"FSK_Demod:inst2\|cnt\[4\]\" and destination pin or register \"FSK_Demod:inst2\|m\[0\]\" for clock \"clk\" (Hold time is 45 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "2.982 ns + Largest " "Info: + Largest clock skew is 2.982 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.573 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 5.573 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.985 ns) 0.985 ns clk 1 CLK PIN_32 9 " "Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_32; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 128 -120 48 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.940 ns) + CELL(0.970 ns) 2.895 ns FSK_Mod:inst1\|FSK_out 2 REG LCFF_X1_Y5_N27 2 " "Info: 2: + IC(0.940 ns) + CELL(0.970 ns) = 2.895 ns; Loc. = LCFF_X1_Y5_N27; Fanout = 2; REG Node = 'FSK_Mod:inst1\|FSK_out'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.910 ns" { clk FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.189 ns) + CELL(0.000 ns) 4.084 ns FSK_Mod:inst1\|FSK_out~clkctrl 3 COMB CLKCTRL_G2 3 " "Info: 3: + IC(1.189 ns) + CELL(0.000 ns) = 4.084 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'FSK_Mod:inst1\|FSK_out~clkctrl'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.189 ns" { FSK_Mod:inst1|FSK_out FSK_Mod:inst1|FSK_out~clkctrl } "NODE_NAME" } } { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.823 ns) + CELL(0.666 ns) 5.573 ns FSK_Demod:inst2\|m\[0\] 4 REG LCFF_X1_Y5_N29 3 " "Info: 4: + IC(0.823 ns) + CELL(0.666 ns) = 5.573 ns; Loc. = LCFF_X1_Y5_N29; Fanout = 3; REG Node = 'FSK_Demod:inst2\|m\[0\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.489 ns" { FSK_Mod:inst1|FSK_out~clkctrl FSK_Demod:inst2|m[0] } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.621 ns ( 47.03 % ) " "Info: Total cell delay = 2.621 ns ( 47.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.952 ns ( 52.97 % ) " "Info: Total interconnect delay = 2.952 ns ( 52.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.573 ns" { clk FSK_Mod:inst1|FSK_out FSK_Mod:inst1|FSK_out~clkctrl FSK_Demod:inst2|m[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "5.573 ns" { clk {} clk~combout {} FSK_Mod:inst1|FSK_out {} FSK_Mod:inst1|FSK_out~clkctrl {} FSK_Demod:inst2|m[0] {} } { 0.000ns 0.000ns 0.940ns 1.189ns 0.823ns } { 0.000ns 0.985ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.591 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.591 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.985 ns) 0.985 ns clk 1 CLK PIN_32 9 " "Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_32; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 128 -120 48 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.940 ns) + CELL(0.666 ns) 2.591 ns FSK_Demod:inst2\|cnt\[4\] 2 REG LCFF_X1_Y5_N15 3 " "Info: 2: + IC(0.940 ns) + CELL(0.666 ns) = 2.591 ns; Loc. = LCFF_X1_Y5_N15; Fanout = 3; REG Node = 'FSK_Demod:inst2\|cnt\[4\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.606 ns" { clk FSK_Demod:inst2|cnt[4] } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.651 ns ( 63.72 % ) " "Info: Total cell delay = 1.651 ns ( 63.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.940 ns ( 36.28 % ) " "Info: Total interconnect delay = 0.940 ns ( 36.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.591 ns" { clk FSK_Demod:inst2|cnt[4] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.591 ns" { clk {} clk~combout {} FSK_Demod:inst2|cnt[4] {} } { 0.000ns 0.000ns 0.940ns } { 0.000ns 0.985ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.573 ns" { clk FSK_Mod:inst1|FSK_out FSK_Mod:inst1|FSK_out~clkctrl FSK_Demod:inst2|m[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "5.573 ns" { clk {} clk~combout {} FSK_Mod:inst1|FSK_out {} FSK_Mod:inst1|FSK_out~clkctrl {} FSK_Demod:inst2|m[0] {} } { 0.000ns 0.000ns 0.940ns 1.189ns 0.823ns } { 0.000ns 0.985ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.591 ns" { clk FSK_Demod:inst2|cnt[4] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.591 ns" { clk {} clk~combout {} FSK_Demod:inst2|cnt[4] {} } { 0.000ns 0.000ns 0.940ns } { 0.000ns 0.985ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.939 ns - Shortest register register " "Info: - Shortest register to register delay is 2.939 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FSK_Demod:inst2\|cnt\[4\] 1 REG LCFF_X1_Y5_N15 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y5_N15; Fanout = 3; REG Node = 'FSK_Demod:inst2\|cnt\[4\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_Demod:inst2|cnt[4] } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.650 ns) + CELL(0.206 ns) 0.856 ns FSK_Demod:inst2\|LessThan0~108 2 COMB LCCOMB_X1_Y5_N4 1 " "Info: 2: + IC(0.650 ns) + CELL(0.206 ns) = 0.856 ns; Loc. = LCCOMB_X1_Y5_N4; Fanout = 1; COMB Node = 'FSK_Demod:inst2\|LessThan0~108'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.856 ns" { FSK_Demod:inst2|cnt[4] FSK_Demod:inst2|LessThan0~108 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.362 ns) + CELL(0.370 ns) 1.588 ns FSK_Demod:inst2\|LessThan0~109 3 COMB LCCOMB_X1_Y5_N2 4 " "Info: 3: + IC(0.362 ns) + CELL(0.370 ns) = 1.588 ns; Loc. = LCCOMB_X1_Y5_N2; Fanout = 4; COMB Node = 'FSK_Demod:inst2\|LessThan0~109'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.732 ns" { FSK_Demod:inst2|LessThan0~108 FSK_Demod:inst2|LessThan0~109 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.037 ns) + CELL(0.206 ns) 2.831 ns FSK_Demod:inst2\|m\[0\]~206 4 COMB LCCOMB_X1_Y5_N28 1 " "Info: 4: + IC(1.037 ns) + CELL(0.206 ns) = 2.831 ns; Loc. = LCCOMB_X1_Y5_N28; Fanout = 1; COMB Node = 'FSK_Demod:inst2\|m\[0\]~206'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.243 ns" { FSK_Demod:inst2|LessThan0~109 FSK_Demod:inst2|m[0]~206 } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.939 ns FSK_Demod:inst2\|m\[0\] 5 REG LCFF_X1_Y5_N29 3 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 2.939 ns; Loc. = LCFF_X1_Y5_N29; Fanout = 3; REG Node = 'FSK_Demod:inst2\|m\[0\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { FSK_Demod:inst2|m[0]~206 FSK_Demod:inst2|m[0] } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 30.28 % ) " "Info: Total cell delay = 0.890 ns ( 30.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.049 ns ( 69.72 % ) " "Info: Total interconnect delay = 2.049 ns ( 69.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.939 ns" { FSK_Demod:inst2|cnt[4] FSK_Demod:inst2|LessThan0~108 FSK_Demod:inst2|LessThan0~109 FSK_Demod:inst2|m[0]~206 FSK_Demod:inst2|m[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.939 ns" { FSK_Demod:inst2|cnt[4] {} FSK_Demod:inst2|LessThan0~108 {} FSK_Demod:inst2|LessThan0~109 {} FSK_Demod:inst2|m[0]~206 {} FSK_Demod:inst2|m[0] {} } { 0.000ns 0.650ns 0.362ns 1.037ns 0.000ns } { 0.000ns 0.206ns 0.370ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 26 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.573 ns" { clk FSK_Mod:inst1|FSK_out FSK_Mod:inst1|FSK_out~clkctrl FSK_Demod:inst2|m[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "5.573 ns" { clk {} clk~combout {} FSK_Mod:inst1|FSK_out {} FSK_Mod:inst1|FSK_out~clkctrl {} FSK_Demod:inst2|m[0] {} } { 0.000ns 0.000ns 0.940ns 1.189ns 0.823ns } { 0.000ns 0.985ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.591 ns" { clk FSK_Demod:inst2|cnt[4] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.591 ns" { clk {} clk~combout {} FSK_Demod:inst2|cnt[4] {} } { 0.000ns 0.000ns 0.940ns } { 0.000ns 0.985ns 0.666ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.939 ns" { FSK_Demod:inst2|cnt[4] FSK_Demod:inst2|LessThan0~108 FSK_Demod:inst2|LessThan0~109 FSK_Demod:inst2|m[0]~206 FSK_Demod:inst2|m[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.939 ns" { FSK_Demod:inst2|cnt[4] {} FSK_Demod:inst2|LessThan0~108 {} FSK_Demod:inst2|LessThan0~109 {} FSK_Demod:inst2|m[0]~206 {} FSK_Demod:inst2|m[0] {} } { 0.000ns 0.650ns 0.362ns 1.037ns 0.000ns } { 0.000ns 0.206ns 0.370ns 0.206ns 0.108ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}