fsk.map.qmsg

通信系统的FSK调制程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 12 10:23:21 2008 " "Info: Processing started: Thu Jun 12 10:23:21 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off FSK -c FSK " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FSK -c FSK" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FSK_Mod.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file FSK_Mod.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FSK_Mod-behave " "Info: Found design unit 1: FSK_Mod-behave" {  } { { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 FSK_Mod " "Info: Found entity 1: FSK_Mod" {  } { { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Carrier.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Carrier.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Carrier-behave " "Info: Found design unit 1: Carrier-behave" {  } { { "Carrier.vhd" "" { Text "E:/My_Design/FPGA/FSK/Carrier.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 Carrier " "Info: Found entity 1: Carrier" {  } { { "Carrier.vhd" "" { Text "E:/My_Design/FPGA/FSK/Carrier.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FSK.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file FSK.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 FSK " "Info: Found entity 1: FSK" {  } { { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FSK_Demod.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file FSK_Demod.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FSK_Demod-behave " "Info: Found design unit 1: FSK_Demod-behave" {  } { { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 FSK_Demod " "Info: Found entity 1: FSK_Demod" {  } { { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "FSK " "Info: Elaborating entity \"FSK\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FSK_Mod FSK_Mod:inst1 " "Info: Elaborating entity \"FSK_Mod\" for hierarchy \"FSK_Mod:inst1\"" {  } { { "FSK.bdf" "inst1" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 88 328 472 216 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Carrier Carrier:inst " "Info: Elaborating entity \"Carrier\" for hierarchy \"Carrier:inst\"" {  } { { "FSK.bdf" "inst" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 104 112 208 200 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FSK_Demod FSK_Demod:inst2 " "Info: Elaborating entity \"FSK_Demod\" for hierarchy \"FSK_Demod:inst2\"" {  } { { "FSK.bdf" "inst2" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 72 704 832 168 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "cnt FSK_Demod.vhd(26) " "Warning (10492): VHDL Process Statement warning at FSK_Demod.vhd(26): signal \"cnt\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 26 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "Demod FSK_Demod.vhd(23) " "Warning (10631): VHDL Process Statement warning at FSK_Demod.vhd(23): inferring latch(es) for signal or variable \"Demod\", which holds its previous value in one or more paths through the process" {  } { { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 23 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "Demod FSK_Demod.vhd(23) " "Info (10041): Inferred latch for \"Demod\" at FSK_Demod.vhd(23)" {  } { { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 23 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "Carrier:inst\|cnt\[0\] FSK_Demod:inst2\|cnt\[0\] " "Info: Duplicate register \"Carrier:inst\|cnt\[0\]\" merged to single register \"FSK_Demod:inst2\|cnt\[0\]\"" {  } { { "Carrier.vhd" "" { Text "E:/My_Design/FPGA/FSK/Carrier.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Carrier:inst\|cnt\[1\] FSK_Demod:inst2\|cnt\[1\] " "Info: Duplicate register \"Carrier:inst\|cnt\[1\]\" merged to single register \"FSK_Demod:inst2\|cnt\[1\]\"" {  } { { "Carrier.vhd" "" { Text "E:/My_Design/FPGA/FSK/Carrier.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Carrier:inst\|cnt\[2\] FSK_Demod:inst2\|cnt\[2\] " "Info: Duplicate register \"Carrier:inst\|cnt\[2\]\" merged to single register \"FSK_Demod:inst2\|cnt\[2\]\"" {  } { { "Carrier.vhd" "" { Text "E:/My_Design/FPGA/FSK/Carrier.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Carrier:inst\|cnt\[3\] FSK_Demod:inst2\|cnt\[3\] " "Info: Duplicate register \"Carrier:inst\|cnt\[3\]\" merged to single register \"FSK_Demod:inst2\|cnt\[3\]\"" {  } { { "Carrier.vhd" "" { Text "E:/My_Design/FPGA/FSK/Carrier.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Carrier:inst\|cnt\[4\] FSK_Demod:inst2\|cnt\[4\] " "Info: Duplicate register \"Carrier:inst\|cnt\[4\]\" merged to single register \"FSK_Demod:inst2\|cnt\[4\]\"" {  } { { "Carrier.vhd" "" { Text "E:/My_Design/FPGA/FSK/Carrier.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Carrier:inst\|cnt\[5\] FSK_Demod:inst2\|cnt\[5\] " "Info: Duplicate register \"Carrier:inst\|cnt\[5\]\" merged to single register \"FSK_Demod:inst2\|cnt\[5\]\"" {  } { { "Carrier.vhd" "" { Text "E:/My_Design/FPGA/FSK/Carrier.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Carrier:inst\|cnt\[6\] FSK_Demod:inst2\|cnt\[6\] " "Info: Duplicate register \"Carrier:inst\|cnt\[6\]\" merged to single register \"FSK_Demod:inst2\|cnt\[6\]\"" {  } { { "Carrier.vhd" "" { Text "E:/My_Design/FPGA/FSK/Carrier.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Carrier:inst\|cnt\[7\] FSK_Demod:inst2\|cnt\[7\] " "Info: Duplicate register \"Carrier:inst\|cnt\[7\]\" merged to single register \"FSK_Demod:inst2\|cnt\[7\]\"" {  } { { "Carrier.vhd" "" { Text "E:/My_Design/FPGA/FSK/Carrier.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 2 " "Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Carrier:inst\|cnt\[23\] " "Info: Register \"Carrier:inst\|cnt\[23\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Carrier:inst\|cnt\[24\] " "Info: Register \"Carrier:inst\|cnt\[24\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "44 " "Info: Implemented 44 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "3 " "Info: Implemented 3 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "39 " "Info: Implemented 39 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "162 " "Info: Allocated 162 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 12 10:23:23 2008 " "Info: Processing ended: Thu Jun 12 10:23:23 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}